Journal of Institute of Control, Robotics and Systems (제어로봇시스템학회논문지)

Institute of Control, Robotics and Systems (제어로봇시스템학회)
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A SEC-DED Implementation Using FPGA for the Satellite System

위성체용 2비트 오류검출 및 1비트 정정 FPGA 구현

  • No, Yeong-Hwan (Dept.of Computer Electronics Information Engineering, Woosong Information college) ;
  • Lee, Sang-Yong (Dept.of Computer Electronics Information Engineering, Woosong Information college)
  • 노영환 (우송대학교 컴퓨터전자정보공학부) ;
  • 이상용 (우송대학교 컴퓨터전자정보공학부)
  • Published : 2000.02.01
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Abstract

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

Keywords

References

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