A new synthesis technique of sequential circuits for low power and testing

Cho, Sang-Wook;Park, Sung-Ju

  • Published : 20040200

Abstract

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on the state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan flip-flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows significant improvement in power dissipation with comparable testabilities for benchmark circuits.

Keywords

References

  1. C.P. Singh, S. Roy, Current Appl. Phys. 3 (2003) 163–169.
  2. P. Kalla, M.J. Ciesielski, in: Proc. Int. Test Conf., November 1998, pp. 651–657.
  3. X. Du, G. Hachtel, B. Lin, A. Richard Newton, IEEE Trans. CAD 10(1) (1991) 28–38.
  4. S. Yang, M.J. Ciesielski, IEEE Trans. CAD 10(1) (1991) 4–12.
  5. K.T. Cheng, V.D. Agrawal, in: Proc. ICCAD, 1989, pp. 358–361.
  6. G. De Micheli, IEEE Trans. CAD 5 (1986) 597–616.
  7. R.K. Brayton, G.D. Hatchel, C.T. McMullen, A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic, Norwell, MA, 1984.
  8. Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1978.
  9. E. Olson, S.M. Kang, in: Proc. IEEE Int. Workshop Low Power Design, April 1995, pp. 63–68.
  10. V. Veeramachaneni, A. Tyagi, S. Rajgopal, in: Proc. IEEE Int. Symp. Low Power Design, April 1995, pp. 173–178.
  11. S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, in: Sixth Asian Test Symp. (ATS '97) Proc., 1997, pp. 30–35.
  12. L. Benini, G. De Micheli, IEEE J. Solid-State Circuits 30(1995) 258–268.