Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design of 250-MSamples/s 8-Bit Folding Analog to Digital Converter using Transistor Differential Pair Folding Technique

트랜지스터 차동쌍 폴딩 기법을 적용한 250-MSamples/s 8-비트 폴딩 아날로그-디지털 변환기의 설계

  • 이돈섭 (두원공과대학 소프트웨어개발과) ;
  • 곽계달 (한양대학교 전자전기컴퓨터공학부)
  • Published : 2004.11.01
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Abstract

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

본 논문에서는 저 전력, 고속 동작을 위하여 트랜지스터 차동쌍 폴딩 회로를 사용하는 CMOS 폴딩 ADC를 설계하였다. 본 논문에서는 제안한 트랜지스터 차동쌍 폴딩 회로에 대한 동작원리와 기존의 폴딩 회로에 비해 어떤 장점을 가지고 있는지 설명한다. 이 회로를 적용하여 설계한 ADC에서는 폴딩신호를 처리하기 위하여 16 개의 정밀한 전압비교기와 32 개의 인터폴레이션 저항을 사용하므로 저 전력, 고속동작이 가능하고, 작은 칩 면적으로 제작할 수 있다. 설계공정은 0.25㎛ double-poly 2metal n-well CMOS 공정을 사용하였다. 모의실험결과 2.5V 전원전압을 인가하고 250MHz의 클럭 주파수에서 45mW의 전력을 소비하였으며 측정값을 통하여 계산된 INL은 ±0.15LSB, DNL은 ±0.15LSB, SNDR은 10MHz 입력신호에서 50dB로 측정되었다.

Keywords

References

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