JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Development of Embedded Non-Volatile FRAMs for High Performance Smart Cards

  • Lee, Kang-Woon (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Jeon, Byung-Gil (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Min, Byung-Jun (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Oh, Seung-Gyu (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Lee, Han-Ju (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Lim, Woo-Taek (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Cho, Sung-Hee (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Jeong, Hong-Sik (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Chung, Chil-Hee (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Kim, Ki-Nam (ATD Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
  • Published : 2004.12.31
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Abstract

Nonvolatile FRAMs with a design rule of 0.18 ${\mu}m$ were developed for the high performance smart card. A 1Mb FRAM was embedded in place of an EEPROM and a 64Kb FRAM was embedded in place of a. SRAM. It was confirmed that the FRAMs performed the roles of the EEPROM and SRAM successfully using the asynchronous write/read operation method and the one time programming (OTP) scheme. The cycle time of the FRAM was 10 MHz, which remarkably improved the write performance of the smart card in comparison with that of the conventional smart card with an EEPROM. Additionally, a simple and smart bit-line reference scheme for the future FRAM device having a 1T1C cell type was proposed.

Keywords

References

  1. J. Yamada, et al., 'A 128Kb FeRAM Macro for a Contact/Contactless Smart Card Microcontroller', ISSCC Digest of Technical Papers, pp. 270-271, 2000
  2. M. K Choi et al., 'A $0.25-{\mu}m$ 3.0-V 1T1C 32-Mb Nonvolatile Ferroelectric RAM with Address Transition Detector and Current Forcing Latch Sense Amplifier Scheme', J. Solid-State Circuits, Vol. 37, pp. 1472-1478, November 2002 https://doi.org/10.1109/JSSC.2002.802357
  3. B. G Jeon, et al., 'A $0.4{\mu}m$ 3.3 V 1T1C 4 Mb nonvolatile ferroelectric RAM with fixed bit-line reference voltage scheme and data protection circuit', ISSCC Digest of Technical Papers, pp. 272-273, 2000