The Transactions of the Korean Institute of Electrical Engineers P (전기학회논문지P)

The Korean Institute of Electrical Engineers (대한전기학회)
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Fault Location Algorithm with Ground Capacitance Compensation for Long Parallel Transmission Line

장거리 병렬 송전선로용 대지 정전용량 보상에 의한 고장점 표정 알고리즘

  • Published : 2005.12.31
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Abstract

This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

Keywords

References

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