ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder

  • Received : 2005.01.31
  • Published : 2005.10.31
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Abstract

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

Keywords

References

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