Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Design and fabrication of the Built-in Testing Circuit for Improving IC Reliability

IC 신뢰성 향상을 위한 내장형 고장검출 회로의 설계 및 제작

  • 유장우 (고려대학교 전기공학과) ;
  • 김후성 (삼성전자(주) 메모리 사업부) ;
  • 윤지영 (고려대학교 전기공학과) ;
  • 황상준 (고려대학교 전기공학과) ;
  • 성만영 (고려대학교 전기공학과)
  • Published : 2005.05.01
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Abstract

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

Keywords

References

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