Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Trade-off Characteristic between Gate Length Margin and Hot Carrier Lifetime by Considering ESD on NMOSFETs of Submicron Technology

  • Joung, Bong-Kyu (Nano Electronic Future Technology Laboratory, Department of Electrical and Electronics Engineering, Chung Ang University) ;
  • Kang, Jeong-Won (Nano Electronic Future Technology Laboratory, Department of Electrical and Electronics Engineering, Chung Ang University) ;
  • Hwang, Ho-Jung (Nano Electronic Future Technology Laboratory, Department of Electrical and Electronics Engineering, Chung Ang University) ;
  • Kim, Sang-Yong (Department of Electrical and Electronics Engineering, Chung Ang University) ;
  • Kwon, Oh-Keun (Department of Internet Information, Se Myung University)
  • Published : 2006.02.01
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Abstract

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

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References

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