Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of an 1.8V 6-bit 100MS/s 5mW CMOS A/D Converter with Low Power Folding-Interpolation Techniques

저 전력 Folding-Interpolation기법을 적용한 1.8V 6-bit 100MS/s 5mW CMOS A/D 변환기의 설계

  • Moon Jun-Ho (Dept. of Semiconductor Science, Dongguk University) ;
  • Hwang Sang-Hoon (Dept. of Semiconductor Science, Dongguk Univeristy) ;
  • Song Min-Kyu (Dept. of Semiconductor Science, Dongguk University)
  • 문준호 (동국대학교 반도체과학과) ;
  • 황상훈 (동국대학교 반도체과학과) ;
  • 송민규 (동국대학교 반도체과학과)
  • Published : 2006.08.01
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Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.

본 논문에서는, 1.8V 6-bit 100MSPS CMOS A/D 변환기를 제안한다. 제안하는 A/D 변환기는 저 전력소모를 위해 폴딩 구조의 A/D 변환기로 구현되었으며, 특히 전압구동 인터폴레이션 기법을 사용하여 전력소모를 최소화하였다. 또한 전체 A/D 변환기의 전력소모 감소를 위해 새로운 폴더 감소회로를 제안하여 기존의 폴딩 A/D 변환기에 비해 폴더 및 프리앰프 수를 절반으로 줄였고, 새로운 프리앰프 평균화 기법을 제안하여 전체 A/D 변환기의 성능을 향상시켰다. 설계된 A/D 변환기는 100MSPS의 변환속도에서 50MHz의 ERBW를 가지며, 이때의 전력소모는 4.38mW로 나타난다. 또한 측정결과 FoM은 0.93pJ/convstep의 우수한 성능 지표를 갖으며, INL 및 DNL은 각각 ${\pm}0.5 LSB$ 이내의 측정결과를 보였다. 제안하는 A/D 변환기는 0.18um CMOS공정으로 제작되었고 유효 칩 면적은 $0.28mm^2$ 이다.

Keywords

References

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