JSTS:Journal of Semiconductor Technology and Science

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Tunnel Barrier Engineering for Non-Volatile Memory

  • Jung, Jong-Wan (Department of NanoScience and Technology, Sejong University) ;
  • Cho, Won-Ju (Department of Electronic Materials Engineering, Kwangwoon University)
  • Published : 2008.03.30
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Abstract

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

Keywords

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