DOI QR코드

DOI QR Code

Study of Thermal Stability of Ni Silicide using Ni-V Alloy

  • Zhong, Zhun (Department of Electrical Engineering, Chungnam National University) ;
  • Oh, Soon-Young (Department of Electrical Engineering, Chungnam National University) ;
  • Lee, Won-Jae (Department of Electrical Engineering, Chungnam National University) ;
  • Zhang, Ying-Ying (Department of Electrical Engineering, Chungnam National University) ;
  • Jung, Soon-Yen (Department of Electrical Engineering, Chungnam National University) ;
  • Li, Shi-Guang (Department of Electrical Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Department of Electrical Engineering, Chungnam National University) ;
  • Wang, Jin-Suk (Department of Electrical Engineering, Chungnam National University) ;
  • Lee, Hi-Deok (Department of Electrical Engineering, Chungnam National University) ;
  • Kim, Yeong-Cheol (Department of Materials Engineering, Korea University of Technology and Education)
  • Published : 2008.04.30

Abstract

In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

Keywords

References

  1. Zhang S. L. and Ostling M., "Metal silicides in CMOS technology : Past, present and future trends", Critical Reviews in Solid State and Materials Sciences, Vol. 28, No. 1, p. 1, 2004 https://doi.org/10.1080/10408430390802431
  2. T. Morimoto, T. Ohguro, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, I. Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsuma, and H. Iwai, "Self-aligned nickel-mono-silicide technology for high-speed deepsubmicrometer logic CMOS ULSI", IEEE Transaction On Electron Devices, Vol. 42, No. 5, p. 915, 1995 https://doi.org/10.1109/16.381988
  3. C. Y. Lin, W. J. Chen, C. H. Lai, A. Chin, and J. Liu, "Formation of Ni germano-silicide on single crystalline Si/sub 0.3/Ge/sub 0.7/Si", IEEE Electron Device Letters, Vol. 23, No. 8, p. 464, 2002 https://doi.org/10.1109/LED.2002.801288
  4. H. Iwai, T. Ohguro, and S. I. Ohmi, "NiSi salicide technology for scaled CMOS", Microelectron. Eng., Vol. 60, p. 157, 2002 https://doi.org/10.1016/S0167-9317(01)00684-0
  5. Lauwers A., Streegen A., de Potter M., Lindsay R., Satta A., Bender H., and Maex K., "Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 um technologies", Journal of Vacuum Science & Technology B, Vol. 19, No. 6, p. 2026, 2001 https://doi.org/10.1116/1.1409389
  6. Iwai H., Ohguro T., and Ohmi S. I., "NiSi salicide technology for scaled CMOS", Microelectronic Engineering, Vol. 60, p. 157, 2002 https://doi.org/10.1016/S0167-9317(01)00684-0
  7. C. J. Choi, S. A. Song, Y. W. Ok, and T. Y. Seong, "Nickel-silicidation process using hydrogen implantation", Electronics Letters, Vol. 40, No. 6, p. 391, 2004 https://doi.org/10.1049/el:20040251
  8. M. C. Sun, M. J. Kim, J. H. Ku, K. J. Roh, C. S. Kim, S. P. Youn, S. W. Jung, S. Choi, N. I. Lee, H. K. Kang, and K. P. Suh, "Thermally robust Ta-doped NiSALICIDE process promising for sub-50 nm CMOSFETs", 2003 Symposium on VLSI Technology Digest of Technical Papers, p. 81, 2003
  9. P. S. Lee, D. Mangelinck, K. L. Pey, J. Ding, D. Z. Chi, T. Osipowicz, J. Y. Dai, and A. See, "Enhanced stability of Ni monosilicide on MOSFETs poly-Si gate stack", Microelectronic Engineering, Vol. 60, Issues 1-2, p. 171, 2002 https://doi.org/10.1016/S0167-9317(01)00592-5
  10. J. G. Yun, S. Y. Oh, B. F. Huang, H. H. Ji, Y. G. Kim, S. H. Park, H. S. Lee, D. B. Kim, U. S. Kim, H. S. Cha, S. B. Hu, J. G. Lee, S. K. Baek, H. S. Hwang, and H. D. Lee, "Highly thermal robust NiSi for nanoscale MOSFETs utilizing a novel hydrogen plasma immersion ion implantation and Ni-Co-TIN tri-layer", IEEE Electron Device Letters, Vol. 26, No. 2, p. 90, 2005 https://doi.org/10.1109/LED.2004.841863

Cited by

  1. Reduction of Barrier Height between Ni-silicide and p+ Source/drain for High Performance PMOSFET vol.22, pp.6, 2009, https://doi.org/10.4313/JKEM.2009.22.6.457