JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs

  • Sharma, Sudhansh (School of Computers and Information Sciences, Indira Gandhi National Open University) ;
  • Kumar, Pawan (Department of Physics, M.M.H. College (Affiliated to Chaudhary Charan Singh University))
  • Published : 2008.06.30
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Abstract

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

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