A Fast Locking Phase Locked Loop with Multiple Charge Pumps

다중 전하펌프를 이용한 고속 위상고정루프

  • Song, Youn-Gui (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University) ;
  • Choi, Young-Shig (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University) ;
  • Ryu, Ji-Goo (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
  • 송윤귀 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 최영식 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 류지구 (부경대학교 전자컴퓨터정보통신공학부)
  • Published : 2009.02.25

Abstract

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

본 논문에서는 다중 전하펌프를 이용하여 빠른 위상고정 시간을 갖는 새로운 위상고정루프를 제안하였다. 제안된 위상고정 루프는 세 개의 전하펌프를 사용하여 루프필터의 실효 커패시턴스와 저항을 위상고정 상태에 따라 각 전하펌프의 전류량 크기와 방향 제어를 통해 증감시킬 수 있다. 위상고정루프의 위상고정 상태에 따라 루프 대역폭을 제어하여 빠른 위상고정 시간을 갖는 위상고정루프를 설계하였다. 또한 전체 칩 영역의 많은 부분을 차지하는 커패시터의 크기를 제안된 구조로 최소화하였다. 저항과 커패시터를 모두 포함한 29.9KHz의 대역폭의 위상고정루프를 $990{\mu}m\;{\times}\;670{\mu}m$ 크기로 설계하였다. 제안된 위상고정 루프는 3.3V $0.35{\mu}m$ CMOS 공정을 이용하여 제작되었다. 851.2MHz 출력 주파수에서 측정된 위상 잡음은 -90.45 dBc/Hz@1MHz이며, 위상고정시간은 $6{\mu}s$ 보다 작은 값을 가진다.

Keywords

References

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