Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Data Level Parallelism for H.264/AVC Decoder on a Multi-Core Processor and Performance Analysis

멀티코어 프로세서에서의 H.264/AVC 디코더를 위한 데이터 레벨 병렬화 성능 예측 및 분석

  • Published : 2009.08.25
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Abstract

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level

최근 멀티코어 프로세서의 이용이 증가함에 따라, 멀티코어환경에서 고성능 H.264/AVC 코덱을 구현하기 위한 다양한 병렬화 기법들이 제안되고 있다. 이러한 기법들은 병렬화 기법 적용 방식에 따라 태스크 레벨 병렬화 기법과 데이터 레벨 병렬화 기법으로 구분된다. 태스크 레벨 병렬화 기법을 이용한 파이프라인 병렬화 기법은 H.264 알고리즘을 파이프라인 단계로 나누어 구현하며, 일반적으로 화면 사이즈가 작고 복잡도가 낮은 비트스트림에 유리하다. 그러나 프로세싱 모듈별 수행시간 차이가 커서 로드밸런싱이 좋지 않고, 파이프라인 단계의 수가 제한적이라 성능 확장성에 제한이 있어 HD 비디오같이 해상도가 큰 비트스트림 처리에는 적합하지 않은 단점이 있다. 본 논문에서는 로드밸런싱 및 성능 확장성을 고려하여 매크로블록 라인 단위로 쓰레드를 할당하는 수평적 데이터 레벨 병렬화 기법을 제안하고, 이에 대한 성능 예측 수식 모델을 통하여 성능을 예상한다. 또한 성능 예측의 정확성을 검증하기 위해 JM 13.2 레퍼런스 디코더에 대한 데이터 레벨 병렬화 기법을 ARM11 MPCore 환경에서 구현하고 이에 대한 성능 검증을 수행하였다. SoCDesigner를 이용한 사이클 단위의 성능 측정 결과, 본 논문에서 제시하는 쓰레드 증가에 대한 병렬화 기법의 성능 변화를 비교적 높은 수준의 정확도로 예측 가능하였다.

Keywords

References

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