JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC

  • Hirai, Naoyuki (College of Systems Innovation Engineering, Graduate School of Advanced Technology and Science, The University of Tokushima) ;
  • Song, Tian (Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, The University of Tokushima) ;
  • Liu, Yizhong (College of Systems Innovation Engineering, Graduate School of Advanced Technology and Science, The University of Tokushima) ;
  • Shimamoto, Takashi (Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, The University of Tokushima)
  • Received : 2009.10.01
  • Published : 2010.03.31
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Abstract

New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.

Keywords

References

  1. Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, “Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264-ISO/IEC 14496-10 AVC),” March 2003.
  2. D. Wu, F. Pan, K. P. Lim, S. Wu, Z. G. Li, X. Lin, S. Rahardja, and C. C. Ko, “Fast intermode decision in H.264/AVC video coding,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.15, No.6, pp.953-958, 2005. https://doi.org/10.1109/TCSVT.2005.848304
  3. B. Kim, S. Song, and C. Cho, “Efficient inter-mode decision based on contextual prediction for the P-slice in H.264/AVC video coding, Proceedings of IEEE International Conference on Image Processing, pp.1333-1336, Oct. 2006.
  4. T. Kuo, and C. Chan, “Fast variable block size motion estimation for H.264 using likelihood and correlation of motion field," IEEE Transactions on Circuits and Systems for Video Technology, Vol.16, No.10, pp.1185-1195, 2006. https://doi.org/10.1109/TCSVT.2006.883512
  5. R. Li, B. Zeng, and M. L. Liuo, “A new three-step search algorithm for block motion estimation,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.4, No.4, pp.438.442, Aug. 1994. https://doi.org/10.1109/76.313138
  6. S. Zhu, and K.-K. Ma, “A new diamond search algorithm for fast block matching motion estimation,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.92, No.2, pp.287.293, Feb. 2000. https://doi.org/10.1109/83.821744
  7. C. Zhu, X. Lin, and L. P. Chau, "Hexagon-based search pattern for fast block motion estimation,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.12, No.5, pp.349.355, Aug. 2002. https://doi.org/10.1109/TCSVT.2002.1003474
  8. J. H. Lee, and N. S. Lee, “Variable block size motion estimation algorithm and its hardware architecture for H.264/AVC,” Proceedings of IEEE International Symposium on Circuits and Systems, Vol.3, pp.741-744, May 2004.
  9. T. C. Chen, S. Y. Chien, Y. W. Huang, C. H. Tsai, C. Y. Chen, and L. G. Chen, “Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, No.6, pp.673-688, 2006. https://doi.org/10.1109/TCSVT.2006.873163
  10. Y. Song, Z. Liu, S. Goto and T. Ikenaga: “Scalable VLSI architecture for variable block size integer motion estimation in H.264/AVC,” IEICE Trans. on Fundamentals, Vol.E89-A, No.4, pp.979-988, 2006. https://doi.org/10.1093/ietfec/e89-a.4.979
  11. Y. Q. Hung, Z. Y. Liu, Y. Song, S. Goto, and T. Ikenaga: “Parallel improved HDTV720p targeted propagate partial SAD architecture for variable block size motion estimation in H.264/AVC,” IEICE Trans. Fundamentals, Vol.E91-A, No.4 April 2008.
  12. L. Zhang, and W. Gao, “Improved FFSBM algorithm and its VLSI architecture for variable block size motion estimation of H.264," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp.445-448, Dec. 2005.
  13. K. Ogata, K. Saito, T. Song, and T. Shimamoto, “Variable search range motion estimation algorithm for H.264/AVC,” IEICE Society Conference, No.A-6-8, Sep. 2006.
  14. T. Kato, T. Song, Y. Z. Liu and T. Shimamoto: “Motion vector predicted variable search range motion estimation algorithm for H.264/AVC,” in Proc. of International Workshop on Vision, Communications and Circuits (IWVCC2008), pp.161-164, Nov. 2008.
  15. Y. Huang, Q. Liu, S. Goto, and T. Ikenaga: “Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architectire for HDTV Applicaion,” IEICE Trans. Fundamentals, Vol.E92-A, No.11 Nov. 2009
  16. JM10 (http://iphome.hhi.de/suehring/tml/)

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