An 1.2V 8-bit 800MSPS CMOS A/D Converter with an Odd Number of Folding Block

홀수개의 폴딩 블록으로 구현된 1.2V 8-bit 800MSPS CMOS A/D 변환기

  • Lee, Dong-Heon (Department of Semiconductor Science, Dongguk University) ;
  • Moon, Jun-Ho (Department of Semiconductor Science, Dongguk University) ;
  • Song, Min-Kyu (Department of Semiconductor Science, Dongguk University)
  • 이동헌 (동국대학교-서울 반도체과학과) ;
  • 문준호 (동국대학교-서울 반도체과학과) ;
  • 송민규 (동국대학교-서울 반도체과학과)
  • Received : 2010.04.15
  • Accepted : 2010.06.30
  • Published : 2010.07.25

Abstract

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

본 논문에서는 기존 폴딩 구조의 A/D 변환기(ADC)가 지닌 경계조건 비대칭 오차를 극복하기 위해 홀수개의 폴딩 블록을 사용한 1.2V 8b 800MSPS CMOS ADC를 제안한다. 제안하는 ADC는 저 전력소모를 위해 폴딩 구조에 저항열 인터폴레이션 기법을 적용하고, 높은 folding rate(FR=9)를 극복하기 위해 cascaded 폴딩 구조를 채택하였다. 특히 폴딩 ADC의 주된 문제인 아날로그 신호의 선형성 왜곡과 offset 오차 감소를 위해 홀수개의 폴딩 블록을 사용하는 신호처리 기법을 제안하였다. 또한 스위치를 사용한 ROM 구조의 인코더를 채택하여 $2^n$ 주기를 가지지 않는 디지털 코드를 일반적인 바이너리 코드로 출력하였다. 제안하는 ADC는 $0.13{\mu}m$ 1P6M CMOS 공정을 사용하여 설계되었으며, 유효면적은 870um$\times$980um이다. 입력주파수 10MHz, 800MHz의 변환속도에서 150mW의 낮은 전력소모 특성을 보이며 SNDR은 44.84dB (ENOB 7.15bit), SFDR은 52.17dB의 측정결과를 확인하였다.

Keywords

Acknowledgement

Supported by : 한국과학재단

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