ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지
DOI QR코드

DOI QR Code

On-Chip Bus Serialization Method for Low-Power Communications

  • Received : 2009.08.02
  • Accepted : 2010.05.25
  • Published : 2010.08.30
Download PDF
⟨ Previous Next ⟩

Abstract

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

Keywords

References

  1. S.J. Lee et al., "An 800 MHz Star-Connected On-Chip Network for Application to Systems on a Chip," ISSCC Dig. Tech. Papers, 2003, pp. 468-469.
  2. S. Kimura et al., "An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators," ISSCC Dig. Tech. Papers, 2003, pp. 390-391.
  3. K. Lee et al., "A 51 mW 1.6 GHz Network for Low-Power Heterogeneous SoC Platform," ISSCC Dig. Tech. Papers, 2004, pp. 152-153.
  4. ARM, "AMBA Specification, Rev. 2.0," 1999.
  5. IBM, "CoreConnect Bus Architecture," 1999.
  6. SuperH, "SuperHyway On-Chip Interconnect Solution," 2003.
  7. Palmchip, "CoreFrame Architecture," 2002.
  8. STMicroelectronics, "STBus Interconnect," 2004.
  9. OpenCores, "Wishbone bus," 2003.
  10. ARM, "AMBA AXI Protocol Specification," 2003.
  11. VSI Alliance, "Virtual Component Interface Standard," 2000.
  12. OCP International Partnership, "Open Core Protocol Specification," 2001.
  13. P.E. Landman and J.M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," IEEE Trans. VLSI Syst., vol. 3, no. 2, June 1995, pp. 173-187. https://doi.org/10.1109/92.386219
  14. M.R. Stan and W.P. Burleson, "Bus-Invert Coding for Low-Power I/O," IEEE Trans. VLSI Syst., vol. 3, no. 1, Mar. 1995, pp. 49-58. https://doi.org/10.1109/92.365453
  15. P. Panda and N. Dutt, "Reducing Address Bus Transitions for Low Power Memory Mapping," Proc. Int. Symp. Design Automation Test Eur., 1996, pp. 63-67.
  16. L. Benini et al., "Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems," Proc. 7th Great Lakes Symp. VLSI, 1997, pp. 77-82.
  17. S. Ramprasad, N. Shanbhag, and I. Hajj, "A Coding Framework for Low-Power Address and Data Busses," IEEE Trans. VLSI Syst., vol. 7, no. 2, June 1999, pp. 212-221. https://doi.org/10.1109/92.766748
  18. Y. Aghaghiri, F. Fallah, and M. Pedram, "Irredundant Address Bus Encoding for Low Power," Proc. Int. Symp. Low-Power Electron. Design, 2001, pp. 182-187.
  19. L. Macchiarulo, E. Macii, and M. Poncino, "Low-Energy for Deep-Submicron Address Buses," Proc. Int. Symp. Low-Power Electron. Design, 2001, pp. 176-181
  20. R.R. Rao et al., "Bus Encoding for Total Power Reduction Using a Leakage-Aware Buffer Configuration," IEEE Trans. VLSI Syst., vol. 13, no. 12, Dec. 2005, pp. 1376-1383. https://doi.org/10.1109/TVLSI.2005.862718
  21. K.M. Lee, S.J. Lee, and H.J. Yoo, "Low-Power Network-On-Chip for High-Performance SoC Design," IEEE Trans. VLSI Syst., vol. 14, Feb. 2006, pp. 148-160. https://doi.org/10.1109/TVLSI.2005.863753
  22. S.M. Kim et al., "Hardware-Software Implementation of MPEG-4 Video Codec," ETRI J., vol. 25, no 6, Dec. 2003, pp. 489-502. https://doi.org/10.4218/etrij.03.0102.0019

Cited by

  1. More efficient home energy management system based on ZigBee communication and infrared remote controls vol.57, pp.1, 2010, https://doi.org/10.1109/tce.2011.5735485
  2. Design methodology for on-chip bus architectures using system-on-chip network protocol vol.6, pp.2, 2010, https://doi.org/10.1049/iet-cds.2011.0054
  3. Characterization of a high-power piezoelectric energy-scavenging device based on PMN-PT piezoelectric single crystals vol.60, pp.2, 2010, https://doi.org/10.3938/jkps.60.230
  4. High-response and low-power-consumption CO micro gas sensor based on nano-powders and a micro-heater vol.60, pp.2, 2010, https://doi.org/10.3938/jkps.60.235
  5. Bandwidth-broadening properties by using a variable width structure in a cantilever-type piezoelectric energy scavenger vol.61, pp.6, 2010, https://doi.org/10.3938/jkps.61.908
  6. A Bus Data Compression Method on a Phase-Based On-Chip Bus vol.12, pp.2, 2010, https://doi.org/10.5573/jsts.2012.12.2.117
  7. Lighting Energy Management System Based on PC’s Power Save Mode vol.253, pp.None, 2010, https://doi.org/10.4028/www.scientific.net/amm.253-255.741