JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Continuous and Accurate PCRAM Current-voltage Model

  • Received : 2011.04.29
  • Published : 2011.09.30
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Abstract

In this paper, we propose a new Verilog-A current-voltage model for multi-level-cell PCRAMs. This model can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states. And, 3 PCRAM operating regions of SET-RESET, Negative Differential Resistance, and strong-ON are unified into one equation in this model thereby any discontinuity that may introduce a convergence problem cannot be found in the new PCRAM model. The percentage error between the measured data and this model is as small as 7.4% on average compared to 60.1% of the previous piecewise model. The parameter extraction which is embedded in the Verilog-A code can be done automatically.

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References

  1. D. Ielmini et al, "Analysis of phase distribution in phase-change non-volatile memories," IEEE Electron Device Lett., Vol.25, No.7, pp.507-509, July, 2004. https://doi.org/10.1109/LED.2004.831219
  2. F. Bedeschi et al, "A bipolar-selected phase-change memory featuring multi-level cell storage," IEEE Journal of Solid-State Circuits, Vol.44, No.1, pp.217-227, Jan., 2009. https://doi.org/10.1109/JSSC.2008.2006439
  3. Y. Liao et al, "Phase change memory modeling using Verilog-A," Behavioral Modeling and Simulation Conf., pp.159-164, 2007.
  4. K. Kwong et al, "Verilog-A model for phase change memory simulation," Solid-State and Integrated- Circuit Tech. Conf., pp.492-495, 2008.
  5. Y. Liao et al, "Temperature-based phase change memory model for pulsing scheme assessment," IEEE Conf. Integrated Circuit Design and Tech., pp.199-202, 2008.
  6. K. Kwong et al, "Circuit implementation to describe the physical behavior of phase change memory," IEEE Conf. Electron Devices and Solid- State Circuits, pp.1-4, 2008.
  7. K. Jo et al, "A compact Verilog-A model for multilevel- cell phase-change rams," IEICE Electronics Express, Vol.6, No.19, pp.1414-1420, Oct., 2009. https://doi.org/10.1587/elex.6.1414
  8. D. Ventrice et al, "A phase change memory compact model for multilevel applications," IEEE Electron Device Lett., Vol.28, No.11, pp.973-975, Nov., 2007. https://doi.org/10.1109/LED.2007.907288
  9. X. Q. Wei et al, "HSPICE macromodel of pcram for binary and multilevel storage," IEEE Trans. Electron Devices, Vol.53, No.1, pp.56-62, Jan., 2006. https://doi.org/10.1109/TED.2005.860645
  10. C. M. Jung et al, "Continous ccurrent-voltage model of multi-level-cell phase-change rams using Verilog-A," in Proc. The 18th Korean Conf. on Semiconductors, pp.569-570, Feb., 2011.
  11. D. Batas and H. Fiedler, "A memristor SPICE implementation and a new approach for magnetic flux-controlled memristor modeling," IEEE Trans. Nanotechnology, Vol.10, No.2, pp.250-255, Mar., 2011 https://doi.org/10.1109/TNANO.2009.2038051

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