Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Wrapper Cell Design for Redundancy TSV Interconnect Test

Redundancy TSV 연결 테스트를 위한 래퍼셀 설계

  • Received : 2010.12.28
  • Accepted : 2011.07.27
  • Published : 2011.08.25
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Abstract

A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

칩의 적층 기술이 적용된 TSV기반 3D IC로 진화함에 따라 새로운 문제점이 발생하게 되었다. Bonding 이후 다이간 TSV가 제대로 연결되었는지 테스트하지만 Redundnacy TSV에 대해서는 테스트하지 않는다. 그러나 더 높은 수율을 얻기 위해서는 redundancy TSV에 대한 연결 테스트를 수행해야 한다. redundancy TSV의 연결을 테스트하고 진단하여 고장 있는 TSV를 대체함으로써 더 높은 수율을 얻을 수 있다. 본 논문에서는 TSV기반 3D IC에서 다이간의 TSV 연결 테스트뿐 아니라 redundancy TSV 테스트를 위한 래퍼셀을 제안하고자 한다. 제안하는 래퍼셀은 하드웨어로 설계하였을 시 기존의 테스트패턴을 그대로 사용할 수 있고, 소프트웨어 설계 시에는 면적을 최소화할 수 있다.

Keywords

References

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