IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
권호 표지
DOI QR코드

DOI QR Code

Design and Verification of High-Performance Parallel Processor Hardware for JPEG Encoder

JPEG 인코더를 위한 고성능 병렬 프로세서 하드웨어 설계 및 검증

  • 김용민 (울산대학교 전기공학부) ;
  • 김종면 (울산대학교 전기공학부)
  • Received : 2011.01.31
  • Accepted : 2011.03.07
  • Published : 2011.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

Keywords

References

  1. 윤현주, "휴대용 멀티미디어 기기에서 메타데이터 활용을 강화한 파일 스스템 구조", 임베디드공학회논문지, 제2권, 제1호, pp. 1-8, 2007년 3월.
  2. 정무경, 박성모, 엄난웅, "병렬 프로세서 기술 및 동향", 전자통신동향분석, 제24권, 제6호, pp.86-93, 2009.
  3. 이재진, 박성모, 엄낙웅, "멀티미디어 애플리케이션 처리를 위한 ASIP", 전자통신동향분석, 제24권, 제6호, pp. 94-98, 2009.
  4. S. Kyo, S. Okazaki, and T. Arai, "Anintegrated memory array processor for embedded image recognition systems", IEEE Trans. Computers, Vol.56, No.5, pp. 622-634, May. 2007. https://doi.org/10.1109/TC.2007.1010
  5. A. A. Abbo, R. P. Kleihorst, V. Choudhary, L. Sevat, Pl Wielage, S. Mouy, B. Vermeulen, and M. Heijligers, "Xetal-II: A 107 GOPS, 600 mW massively parallel processor for video scene analysis", IEEE J. Solid-State Circuits, Vol.43, No.1, pp. 192-201, Jan. 2008. https://doi.org/10.1109/JSSC.2007.909328
  6. 박제호, "허프변환을 이용한 직선요소 검출기반 정지영상 인식자", 임베디드공학회논문지, 제5권, 제3호, pp. 111-117, 2010.
  7. Wallace, G.K., "The JPEG still picture compression standard", IEEE Transactions on Consumer Electronics, Vol.38, No.1, pp. 18-33, Feb. 1992.
  8. W. H. Chen, C. Smith, and S. Fralick, "A Fast computational algorithm for the discrete cosine transform", IEEE Trans. Communications, Vol.25, No.9, pp. 1004-1009, Sep. 2002.
  9. Wastson, B. Andrew, "Image compression using the discrete cosine transform", Mathematical J., Vol.4, No.1, pp. 81-88, 1994.
  10. S. M. Chai, T. Taha, D. S. Wills, J. D. Meindl, "Heterogeneous architecture models for interconnect-motivated system design", IEEE Trans. on VLSI Systems, Vol.8, No.6, pp. 660-670, 2000. https://doi.org/10.1109/92.902260
  11. J. C. Eble, V. K. De, D. S. Wills, J. D. Meindl, "Generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001", Proceedings of the Ninth Annual IEEE International ASIC Conference, pp. 193-196, Sep. 1996.
  12. Antonio Gentile, D. Scott Wills, "Portable video supercomputing", IEEE Trans. Computers, Vol.53, No.8, pp. 960-973, 2004. https://doi.org/10.1109/TC.2004.48
  13. M. H. Sunwoo, J. K. Aggarwal, "A sliding memory plane array processor", IEEE Transactions on Parallel and Distributed System, Vol.4, No.6, pp. 601-612, 1993. https://doi.org/10.1109/71.242162
  14. T. Moriss, E. Fletcher, C. Afghani, S. Issa, K. Connolly, J. C. korta, "A column-based processing array for high speed digital image processing", Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, pp. 42-56, 1999.
  15. TMS320C64x families: http://www.bdti.com/procsum/tic64xx.htm.
  16. Stnplify Userguide: http://www.synopsys.com/Tools/Implementation/FPGAImp
  17. Xilinx Userguide: http://www.xilinx.com/support/doucumentation.user_guides/ug070.pdf