DOI QR코드

DOI QR Code

Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

  • Suh, Chung-Ha (School of Electronic & Electrical Eng., HongIk University)
  • Received : 2011.04.29
  • Published : 2011.06.30

Abstract

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

Keywords

References

  1. Takato H., Sunouchi K., Okabe N., Nitayama A., Hieda K., Horiguchi F., Masuoka F., "High performance CMOS surrounding gate transistor (SGT) for ultra high density LSI's," IEDM Tech. Dig., pp.222-225, 1998.
  2. Sunouchi K., Takato H., Okabe N., Yamada T., Ozaki T., Inoue S., Hashimoto K., Hieda K., Nitayama A., Horiguchi F., Masuoka F., "A surrounding gate transistor (SGT) cell 64/256 Mbit DRAMs," IEDM Tech. Dig., p.23, 1989.
  3. Takato H., Sunouchi K., Okabe N., Nitayama A., Hieda K., Horiguchi F., Masuoka F., "Impact of surrounding gate transistor (SGT) for ultra high density LSIs," IEEE Trans. Electron Devices, Vol.38, pp.573-578, 1991. https://doi.org/10.1109/16.75168
  4. Nitayama H., Takato H., Okabe N., Sunouchi K., Hieda K., Horiguchi F., Masuoka F., "Multi-pillar surrounding gate transistor (M-SGT) for compact and high speed circuits," IEEE Trans. Electron Devices, Vol.38, pp.579-583, 1991. https://doi.org/10.1109/16.75169
  5. Miyano S., Hirose M., Masuoka F., "Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)", IEEE Trans. Electron Devices, Vol.39, pp.1876-1881, 1992. https://doi.org/10.1109/16.144678
  6. Watanabe S., Tsuchida K., Takashima D., Oowaki T., Nitayama A., Hieda K., Takato H., Sunouchi K., Horiguchi F., Ohuchi K., Masuoka F., Hara H., "A novel circuit technology with surround gate transistors (SGT) for ultra-high density DRAM's", IEEE J. Solid State Circuits, Vol.30, pp.960-971, 1995. https://doi.org/10.1109/4.406391
  7. Endoh T., Nakamura T., Masuoka F., "An accurate model of fully-depleted surrounding gate transistor (FD-SGT)", IEICE Trans. Electron., Vol.E80-C, pp.905-910, 1997.
  8. Endoh T., Nakamura T., Masuoka F., "An analytical steady-state current-voltage characteristics of a short channel fully depleted surrounding gate transistor (FD-SGT)", IEICE Trans. Electron., Vol.E80, pp.911-917, 1997.
  9. Auth C.P., Plummer J.D., "Scaling theory for cylindrical, fully-depleted, surrounding gate MOSFET's", IEEE Electron Device Lett., Vol.18, No.2, pp.74-76, 1997. https://doi.org/10.1109/55.553049
  10. Jang S.L., Liu S.S., "An analytical surrounding gate MOSFET model", Solid State Electronics, Vol.42, No.5, pp.721-726, 1998. https://doi.org/10.1016/S0038-1101(97)00243-8
  11. Oh S.H., Monroe D., Hergenrother J.M., "Analytic description of short-channel effects in fullydepleted double-gate and cylindrical, surroundinggate MOSFETs", IEEE Electron Device Lett., Vol.21, No.9, pp.445-447, 2000. https://doi.org/10.1109/55.863106
  12. Kranti A., Haldar S., Gupta R.S., "An accurate 2D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET", Microelectronics Journal, Vol.32, pp.305-313, 2001. https://doi.org/10.1016/S0026-2692(01)00008-8
  13. Kranti A., Haldar S., Gupta R.S., "Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET", Microelectronic Engineering, Vol.56, pp.241-259, 2001. https://doi.org/10.1016/S0167-9317(00)00419-6
  14. Chiang T.K., "A new two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding gate (SG) MOSFETs", Microelectronics Reliability, Vol.47, pp.379-383, 2007. https://doi.org/10.1016/j.microrel.2006.05.016
  15. Murray R. Spiegel, John Liu, Mathematical Handbook of Formulas and Tables, p.33, 1968, 2nd ed., McGraw-Hill
  16. Suh C.H., "A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET", Solid State Electronics, Vol.52, pp.1249-1255, 2008. https://doi.org/10.1016/j.sse.2008.05.014
  17. Suh C.H., "Analytical model for deriving the threshold voltages of a short gate SOI MESFET with vertically non-uniformly doped silicon film", IET Circuits, Devices, and Systems, Vol.4, No.6, pp.525-530, 2010. https://doi.org/10.1049/iet-cds.2009.0307

Cited by

  1. A Compact Model of Gate-Voltage-Dependent Quantum Effects in Short-Channel Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors vol.11, pp.4, 2011, https://doi.org/10.5573/JSTS.2011.11.4.278
  2. Analysis of Subthreshold Swing for Channel Doping of Asymmetric Double Gate MOSFET vol.18, pp.3, 2014, https://doi.org/10.6109/jkiice.2014.18.3.651
  3. Analysis of Subthreshold Swing for Doping Distribution Function of Asymmetric Double Gate MOSFET vol.18, pp.5, 2014, https://doi.org/10.6109/jkiice.2014.18.5.1143
  4. An Analytical Model for Deriving the 3-D Potentials and the Front and Back Gate Threshold Voltages of a Mesa-Isolated Small Geometry Fully Depleted SOI MOSFET vol.12, pp.4, 2012, https://doi.org/10.5573/JSTS.2012.12.4.473