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Accuracy Analysis of Extraction Methods for Effective Channel Length in Deep-Submicron MOSFETs

  • Kim, Ju-Young (Department of Electronic Engineering, Hankuk University of Foreign Studies) ;
  • Choi, Min-Kwon (Department of Electronic Engineering, Hankuk University of Foreign Studies) ;
  • Lee, Seong-Hearn (Department of Electronic Engineering, Hankuk University of Foreign Studies)
  • Received : 2011.05.09
  • Published : 2011.06.30

Abstract

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

Keywords

References

  1. N. Arora, "MOSFET modeling for VLSI simulation : theory and practice," World Scientific, p.468, 2007.
  2. C. T. Yao, I. A. Mack, and H. C. Lin, "Accuracy of effective channel-length extraction using the capacitance method," IEEE Electron Device Lett., Vol.EDL-7, No.4, pp.268-270, Apr., 1986. https://doi.org/10.1109/EDL.1986.26368
  3. Y. Taur, "MOSFET channel length : extraction and interpretation," IEEE Trans. Electron Devices, Vol. 47, No.1, pp.160-170, Jan., 2000. https://doi.org/10.1109/16.817582
  4. S. Lee, "A new RF capacitance method to extract the effective channel length of MOSFET's using Sparameters," in Proc. IEEE Hong Kong Electron Devices Mtg., pp.56-59, June 2000. https://doi.org/10.1109/HKEDM.2000.904215
  5. A. Ferrero and U. Pisani, "QSOLT: A new fast calibration algorithm for two port S parameter measurements," 38th ARFTG Conference Digest, pp. 15-24, Winter 1991. https://doi.org/10.1109/ARFTG.1991.324034
  6. S. Lee, "Effects of pad and interconnection parasitics on forward transit time in HBTs," IEEE Trans. Electron Devices, Vol.46, No.2, pp.275-280, Feb., 1999. https://doi.org/10.1109/16.740889
  7. J.-Y. Kim, B.-H. Ko, M.-K. Choi, and S. Lee, "RF extraction method for source/drain overlap and depletion length of deep-submicron RF MOSFETs using intrinsic gate-bulk capacitance," Electron. Lett., Vol.46, No.23, pp.1566-1568, Nov., 2010. https://doi.org/10.1049/el.2010.2174
  8. Y. Tsividis, "Operation and modeling of the MOS transistor", 2nd ed, McGraw-Hill, p.404, 1999.

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