Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Ti/Cu CMP process for wafer level 3D integration

웨이퍼 레벨 3D Integration을 위한 Ti/Cu CMP 공정 연구

  • Kim, Eunsol (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Lee, Minjae (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Sungdong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Sarah Eunkyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology)
  • 김은솔 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 이민재 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김사라은경 (서울과학기술대학교 NID융합기술대학원)
  • Received : 2012.05.02
  • Accepted : 2012.07.05
  • Published : 2012.09.30
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Abstract

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

Cu 본딩을 이용한 웨이퍼 레벨 적층 기술은 고밀도 DRAM 이나 고성능 Logic 소자 적층 또는 이종소자 적층의 핵심 기술로 매우 중요시 되고 있다. Cu 본딩 공정을 최적화하기 위해서는 Cu chemical mechanical polishing(CMP)공정 개발이 필수적이며, 본딩층 평탄화를 위한 중요한 핵심 기술이라 하겠다. 특히 Logic 소자 응용에서는 ultra low-k 유전체와 호환성이 좋은 Ti barrier를 선호하는데, Ti barrier는 전기화학적으로 Cu CMP 슬러리에 영향을 받는 경우가 많다. 본 연구에서는 웨이퍼 레벨 Cu 본딩 기술을 위한 Ti/Cu 배선 구조의 Cu CMP 공정 기술을 연구하였다. 다마싱(damascene) 공정으로 Cu CMP 웨이퍼 시편을 제작하였고, 두 종류의 슬러리를 비교 분석 하였다. Cu 연마율(removal rate)과 슬러리에 대한 $SiO_2$와 Ti barrier의 선택비(selectivity)를 측정하였으며, 라인 폭과 금속 패턴 밀도에 대한 Cu dishing과 oxide erosion을 평가하였다.

Keywords

References

  1. Y. Ein-Eli and D. Starosvetsky, "Review on copper chemicalmechanical polishing (CMP) and post-CMP cleaning in ultra large system integrated (ULSI)-An electrochemical perspective", Electrochimica Acta, 52, 1825 (2007). https://doi.org/10.1016/j.electacta.2006.07.039
  2. S. Balakumar, X. T. Chen, Y. W. Chen, T. Selvaraj, B. F. Lin, R. Kumar, T. Hara, M. Fujimoto and Y. Shimura, "Peeling and delamination in Cu/SilK process during Cu-CMP", Thin Solid Films, 462/463, 161 (2004). https://doi.org/10.1016/j.tsf.2004.05.090
  3. F. Zhao, L. Economikos, W. Tseng, H-k Kim, E. Engbrecht, T. E. Standaert, J. H. Li, W. P. Liu, M. Chae, L. M. Nicholson and S. Sankaran, "Evaluation of Cu CMP Barrier Slurries for Ultra Low-k dielectric film (k-2.4) for 45nm technology", Proc. International Conference on Planarization/CMP Technology, Oct. 25 -27 (2007).
  4. J. Vaes, F. Sinap, J. L. Hernandez, G. Santoro, O. Nguyen and J. Wang, "CMP of a Ru based layer in an advanced Cu lowk stack", Proc. International Conference on Planarization/ CMP Technology, Oct. 25 -27 (2007).
  5. K. Gottfried, I. Schubert, S. E. Schulz and T. Gessner, "Cu/ barrier CMP on porous low-k based interconnect schemes", Microelectronic Engineering, 83, 2218 (2006). https://doi.org/10.1016/j.mee.2006.10.007
  6. 박점용, 홍의관, 엄대홍, 박진구, "The effects of additives in Cu CMP slurry on polishing" Proc. 2001 KMEPS Fall Technology Symposium, 230 (2001)
  7. W. Wu, H.-J. Wu, G. Dixit, R. Shaviv, M. Gao, T. Mountsier, G. Harm, A. Dulkin, N. Fuchigami, S. K. Kailasam, E. Klawuhn and R. H. Havemann, "Ti-based Barrier for Cu Interconnect Applications", IEEE IITC, 202 (2008).
  8. V. Nguyen, H. VanKranenburg and P. Woerleea, "Dependency of dishing on polish time and slurry chemistry in Cu CMP", Microelectronic Engineering, 50, 403 (2000). https://doi.org/10.1016/S0167-9317(99)00308-1
  9. C. H. Seah, G. Z. You, S. R. Wang, C. Y. Li and R. Kumar, "Impact of electroplated copper thickness on copper CMP and Cu/CoralTM BEOL integration", Microelectronic Engineering, 81, 66 (2005). https://doi.org/10.1016/j.mee.2005.03.040
  10. J. M. Park, Y. Kim, S. D. Kim, J. W. Kim and Y. B. Park, "Wet Etching Characteristics of Cu Surface for Cu-Cu Pattern Direct Bonds", J. Microelectron. Packag. Soc., 19(1), 39 (2012). https://doi.org/10.6117/kmeps.2012.19.1.039
  11. Y. J. Kang, D. H. Eom, J. H. Song and J. G. Park, "The Effect of pH adjustor in Cu Slurry on Cu CMP", PacRim-CMP, 197 (2004).
  12. S. G. Kang, Y. Kim, J. Lee, E. Kim, S. Kim and S. E. Kim, "Fabrication and Reliability of Wafer Level Cu-to-Cu Bonding for 3D Integration", IUMRS_ICA, P0807 (2011).

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