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Design of 100-V Super-Junction Trench Power MOSFET with Low On-Resistance

  • Lho, Young-Hwan (Department of Railroad Electricity and Information Communications, Woosong University) ;
  • Yang, Yil-Suk (Convergence Components & Materials Research Laboratory, ETRI)
  • Received : 2011.06.08
  • Accepted : 2011.07.28
  • Published : 2012.02.01
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Abstract

Power metal-oxide semiconductor field-effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double-diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. To overcome the tradeoff relationship, a super-junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-state resistance of 1.2 $m{\Omega}-cm^2$ at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.

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References

  1. Y. Chen, Y.C. Liang, and G.S. Samudra, "Design of Gradient Oxide-Bypassed Super-Junction Power MOSFET Devices," IEEE Trans., vol. 22, no. 4, July 2007, pp. 1303-1309.
  2. Y. Wang et al., "Gate Enhanced Power UMOSFET with Ultralow On-Resistance," IEEE Electron. Device Lett., vol. 31, no. 4, Apr. 2010, pp. 338-340.
  3. B.J. Baliga, Advanced Power MOSFET Concepts, New York Springer-Science, 2010, pp. 323-354.
  4. J.A. Yedinack et al., "Super-Junction Structures and Fabricating Methodologies for Power Devices," Korean Patent: 10-2010- 0083153.
  5. J. Kim et al., "A Novel Technique for Fabricating High Reliable Trench DMOSFETs Using Self-Align Technique and Hydrogen Annealing," IEEE Trans. Electron Devices, vol. 50, no. 2, 2003, pp. 378-383.
  6. S.-G. Kim et al., "High-Density Nano-Scale N-Channel Trench- Gated MOSFETs Using the Self-aligned Technique," J. Korean Physical Society, vol. 57, no. 4, Oct. 2010, pp. 802-805.
  7. SILVACO TCAD Manual, Atlas, 2011.

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