Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Hardware Design of SURF-based Feature extraction and description for Object Tracking

객체 추적을 위한 SURF 기반 특이점 추출 및 서술자 생성의 하드웨어 설계

  • Do, Yong-Sig (Department of electronics and communication engineering, Kwangwoon University) ;
  • Jeong, Yong-Jin (Department of electronics and communication engineering, Kwangwoon University)
  • 도용식 (광운대학교 전자통신공학과) ;
  • 정용진 (광운대학교 전자통신공학과)
  • Received : 2013.01.25
  • Published : 2013.05.25
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Abstract

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

최근 영상처리 응용의 일환으로 객체 추적 시스템에 많이 활용되는 SURF 알고리즘의 경우 영상의 회전 및 크기 변화에 강인한 특이점을 추출한다는 특징이 있지만 연산이 복잡하고 연산량이 많아 임베디드 환경에서 IP로 사용되기 위해서는 하드웨어 가속기 개발이 필수적이다. 하지만 이 때 요구되는 내부 메모리 사이즈가 매우 크기 때문에 ASIC이나 SoC 시스템으로 개발 할 때 칩 회로 사이즈가 커서 IP의 가치를 떨어뜨리게 된다. 본 논문에서는 하드웨어 가속기 개발 시 회로면적에 효율적인 설계를 위해 내부 블록메모리 사용량을 줄이고 외부 메모리와 DMA를 사용하여 세분화된 Sub-IP 구조로 설계하는 것에 대해 연구하고 간단한 객체 추적 알고리즘을 개발하여 그 결과를 적용하였다. ARM Cortex-M0, AHB-lite, APB, DMA, SDRAM Controller로 구성된 시스템 환경에서 실험 결과 VGA(640x480)영상에서 SURF 알고리즘의 처리속도는 약 31frame/sec, 블록 메모리의 크기는 81Kbytes, 30nm 공정에서 회로의 크기는 약 74만 게이트 크기로 SoC 칩의 하드웨어 IP로 활용이 가능하였다. SURF와 비슷한 영상처리 알고리즘에서도 본 논문에서 제안하는 설계방법을 적용하면 타겟 어플리케이션에 효율적인 하드웨어 설계를 할 수 있을 것으로 기대된다.

Keywords

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