1. Introduction

The primary challenges faced in scaling a complementary metal oxide semiconductor (CMOS) device are to ensure the increased functionality per unit cost and improvement in the performance of device. Several technologies are proposed to keep up the scaling law proposed by Gordon Moore. In order to fulfill the scaling law, various device structures are required for maintaining the device characteristics accurately. These device structures include double gate (DG) MOSFETs, dual material gate (DMG) MOSFETs, surrounding gate (SG) MOSFETs, and dual material surrounding gate (DMSG) MOSFETs device. The key factors that limit the performance of MOS devices are increased short channel effects (SCE) and very high leakage current. In recent years, a number of non-classical MOS device structures have been proposed to overcome the SCEs of CMOS technology in the nanoscale region. But in these non classical devices, the supply voltage cannot be reduced further because of the Subthreshold Swing (SS) being limited to 60 mV/decade [1,2] at the room temperature.

Tunnel field-effect transistor has been considered as a best alternative device in the standard CMOS for lowpower applications. Due to the built-in tunnel barrier, the TFET device does not suffer from short channel effects, when compared to the conventional planar MOSFET device.

TFET has several superior properties such as, the subthreshold swing is smaller than 60 mV/decade at room temperature [3], which is the physical limit of the MOSFET. In addition, tunnel field effect transistors (TFETs) show a very small leakage current, in the range of femto amperes (fA) [4] when the device is turned off. Also TFET offers much smaller Vt roll-off while scaling because threshold voltage depends on the band bending in small tunnel region, but not the whole channel region. Apart from all these merits, TFETs suffer from a low ONcurrent (ION). Therefore various techniques to improve the ION in the TFET have been suggested [5], [6]. In order to enhance the ON current (ION), various design improvements in terms of band gap engineering [6], hetero junction TFETs [7] strained silicon [8], novel architectures like carbon nanotube TFETs [9], DG TFET [10] and DMG DGTFETs [11] have been proposed. The above models deal only with simulation and only a few analytical models were proposed. [12-14]. The analytical model provides better understanding of the physical design of the TFETs. Lee [12] proposed a model for potential and electric field for Single Material Gate (SMG) TFET using superposition method. Despite accuracy of this model, it involves a lot of mathematical complexity and makes its understanding difficult. Bardon [14] proposed potential and electric field model for DG TFET using pseudo 2-D solution. 1-D poisson’s equation based modeling of TFET was devised by Verhulst [15]. In this paper, we have proposed a new novel DMG TFET structure which enhances the ION current during device operation

The aim of this work is, to study the potential benefits offered by the DMG TFET by using parabolic approximation technique for the first time, which is simple and accurate. The analytical model is developed using two dimensional solution of Poisson equation. This model is used to calculate the surface potential and electric field distribution in the device under the two metal gates and the drain current IDS is derived from the electric field using Kane’s model. This paper is ordered as follows: Section 2 shows model derivation of this work. The result and discussions are analyzed in Section 3 and Section 4 contains a summary of the conclusions.

2. Model Derivation

The cross section view of a Dual Material Gate TFET is shown in Fig. 1. The source and drain is made of highly doped p-type and n-type regions respectively. The intermediate channel region is made of a moderately doped n-type layer. Silicon-di-oxide (SiO2) is used as the gate dielectric. The gate consists of two materials M1 and M2 with gate lengths L1 and L2 with two different work function Φm1 and Φm2 . Based on the positive or negative potential applied to the gate terminal, the device behaves as n type TFET and p type TFET respectively. If a positive gate voltage is applied, the transistor behaves as a n-TFET and a negative gate voltage is applied, the transistor behaves as a p-TFET. The device physical parameters are summarized in Table 1. Increasing the positive voltage on the gate narrows the energy barrier between the source and intrinsic region. Then electrons tunnel from the valence band of the p-doped source to the conduction band in the intrinsic body and then move toward the n-doped drain by drift diffusion. The bottom of the buried oxide (BOX) layer is grounded. The thickness of the BOX layer (tBOX) is very small, hence the voltage drop across BOX region is negligible.

Fig. 1.Schematic diagram of a DMG TFET

Table 1.The values of parameters used in simulations

2.1 Surface potential

The potential distribution in the gate oxide region is distinguished by two dimensional Poisson’s equation [12],

The potential profile in the vertical direction is assumed to be a second-order polynomial, i.e.,

The boundary conditions in the channel region are:

(a) Electric flux at the front-oxide gate interface is continuous for DMG TFET, therefore

(b) Electric flux at the back gate-oxide and the back channel interface is continuous for both the material

(c) The potential at the source and drain end is

Where Vbi is the built in potential, Eg is Band gap energy, q is elementary charge, VGS is Gate to Source voltage, VDS is Drain to Source voltage, εsi is relative permittivity of silicon and εox is relative permittivity of silicon dioxide.

Since we have two materials in the gate, the potential under Material1 (M1) and Material2 (M2) can be written as

The values of C11(x), C12(x), C21(x), and C22(x) are arbitrary constants which is obtained from the boundary conditions (3-5) and (6).

potential Φs1(𝑥) and Φs2(𝑥) under M1 and M2 can be obtained by solving the Poisson’s equation (1) using boundary conditions (7), (8) and (9), therefore,

where ψg1 = Vgs −Φm1 + χ + Eg/2ψg2 = Vgs −Φm2 + χ + Eg/2

Where the gate work function of metal1 ( Φm1 ) is 4eV and metal2 (Φm2 ) is 4.6eV. χ is the electron affinity. The coefficients of A, B, C and D can be expressed as

2.2 Electric field

The electric-field distribution along the channel length can be obtained by differentiating the surface potential. The lateral electric field can be written as,

The vertical electric field can be written as

2.3 Drain current

The mechanism of flow of current IDS in DMG TFET is based on Band-to-Band Tunneling (BTBT) of electrons from the valance band of the source to the conduction band of the channel region. The tunneling generation rate (G) can be calculated using Kane’s model. The total drain current is computed by integrating the band to band generation rate over the volume of the device. Therefore,

For the calculation of tunneling Generation rate (G), Kane’s Model has been employed [14, 16, 17].

where, │E│ is the magnitude of the electric field which is defined as and Eg is the energy band gap. The parameters used for TCAD simulation are A=8.1×1017eV1/2/cm.s.V2 and B= 3.057×107V/cm-(eV)3/2.

3. Result and Discussion

In order to verify the analytical model, two-dimensional device simulation has been performed by using TCAD Sentaurus. In the simulator Band-to-Band Tunneling is an important parameter considered for analyzing the working of Tunnel FETs. The models available in TCAD to simulate band-to-band tunneling are Kane’s Band-to-Band model, Hurkx’s Band-to-Band model, Schenk’s Band-to- Band model and the dynamic Non Local Band-to-Band model. In our work the Kane’s model is used to evaluate the band-to-band generation rate. It is also compared with the superposition model proposed by M.J.Lee [12] for SMG TFET. At low values of VDS (approximately 0 to 0.5 V), the gate bias induces an accumulation of electronics in the channel region. This leads to reduce the channel resistance. Hence the tunnel width is decreased which in turn increases the electric field across the tunneling junction, leading to a rapid increase in the drain current IDS.

Fig. 2 shows the calculated surface potential profile for different gate voltage of the DMG TFET structure along with the simulated potential profile. As the gate voltage increases, the potential in the lightly doped region increases. There is a step-change of potential along the channel at the interface of Metal1 and Metal2.It is clearly seen from the figure that due to the presence of gate bias, there is momentous change in the potential under the gate metal 1. As a result the gate bias has high influence on tunneling current at source side.

Fig. 2.Surface potential profiles of DMG-TFET for Channel length L=20nm and VDS=0.1V with different gate biases.

Fig. 3 shows the calculated surface potential profile for different drain voltage of the DMG TFET structure along with the simulated potential profile. As the drain voltage increases, the potential in the region under metal2 increases. But there is no significance change in potential under Metal1. Hence Metal1 is screened from the effect of drain voltage. Analytical results are in excellent agreement with simulation results.

Fig. 3.Surface potential profiles of DMG-TFET for channel length L=20nm and VGS=0.1V with different VDS

Fig. 4 shows the calculated and simulated values of the surface potential at VGS=0.3V and VDS=0.1V along the channel length for the DMG TFET and it is also compared with Lee model. Fig. 5 shows the variation of vertical electric field distribution with the channel position for different values of gate voltage. It is evident from the figure that peak of the vertical electric field appears near the tunneling junction. ie., region under metal 1. Due to this effect the tunneling current gets increased. The electric field near the drain decreases with the change in the work function. ie., region under metal 2. The simulation results proved the validity of the model proposed. Fig. 6 shows the modeled and simulated values of the lateral electric field distribution at VGS=0.3V and VDS=0.1V along the channel length for the DMG TFET and it is also compared with the model proposed by Lee for SMG TFET considering the same channel length. The lateral electric field is present on the device at any gate voltage. Analytical results are in excellent agreement with simulation results.

Fig. 4.Surface potential profiles of DMG-TFET and SMG TFET for Channel length L=20nm, VDS=0.1V and VGS=0.3V

Fig. 5.Vertical electric field of DMG-TFET for Channel length L=20nm and VDS=0.1V with different gate biases.

Fig. 6.Lateral electric field of DMG-TFET and SMG TFET for Channel length L=20nm, VDS=0.1V and VGS=0.3V

Fig. 7 shows the ID-VGS characteristics of DMG TFET with modeled and simulated values and it is compared with the model proposed by Lee. The positive values of VGS, electrons tunnel from valence band in p+ source region to conduction band in channel region and the tunneling current gets increased. The device behaves as a N type DMG TFET. The negative values of VGS, electrons tunnel from valence band in channel region to conduction band in n+ drain region and the tunneling current gets increased. The device is behaves as a P type DMG TFET. It is inferred from the figure that our model has higher drive current than SMG TFET. Fig. 8 shows the ID-VDS characteristics of DMG TFET with modeled and simulated values with gate voltages 0.3V and 0.5V respectively. Analytical results are in excellent agreement with simulation results

Fig.7.ID-VGS characteristics of DMG-TFET for channel length L=20nm and VDS=0.1V

Fig.8.ID-VDS characteristics of DMG-TFET for channel length L=20nm with varies gate voltage VGS.

4. Conclusion

In this work the DMG-TFET structure has been analyzed and their performance improvements over different parameters are discussed. The analytical model is based on two-dimensional Poisson’s equation which is solved by using parabolic approximation. The analytical expressions of surface potential, lateral electric field and vertical electric field have been calculated. In this model, components of lateral electric field and vertical electric field can also be used to analytically calculate distribution of tunneling generation rate and numerically extract tunneling current. Based on the generation rate and electric fields, we obtained the IDS-VGS characteristics. From the presented results, it can be concluded that the DMG structure provides wide range of benefits to the TFET performance. The results clearly demonstrate the excellent immunity against SCE offered by the DMG structure while decreasing channel length.