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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Architectural Design Issues in a Clockless 32-Bit Processor Using an Asynchronous HDL

  • Received : 2012.09.07
  • Accepted : 2013.01.11
  • Published : 2013.06.01
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Abstract

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

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References

  1. C.H. Van Bekel et al., "Applications of Asynchronous Circuits," Proc. IEEE, vol. 87, no. 2, Feb. 1999, pp. 223-233. https://doi.org/10.1109/5.740016
  2. C.J. Myers, Asynchronous Circuit Design, NY: John Wiley & Sons, Inc., July 2001.
  3. J. Kessels and R. Marston, "Designing Asynchronous Standby Circuits for a Low-Power Pager," Proc. IEEE, vol. 87, no. 2, Feb. 1999, pp. 257-267. https://doi.org/10.1109/5.740019
  4. B.Z. Tang et al., "A Low Power Asynchronous GPS Baseband Processor," Proc. IEEE 18th Int. Symp. Asynchronous Circuits Syst., 2012, pp. 33-40.
  5. S. Bo et al., "Reducing Power Consumption of Floating-Point Multiplier via Asynchronous Technique," Proc. 4th Int. Conf. Comput. Inf. Sci., Aug. 2012, pp. 1360-1363.
  6. Handshake Solutions, TiDE Manual, 2009
  7. Handshake Solutions, Haste Manual, 2009
  8. A. Bink and R. York, "ARM996HS: The First Licensable, Clockless 32-Bit Processor Core," IEEE Micro, vol. 27, no. 2, 2007, pp. 58-68.
  9. A. Takamura et al., "TITAC-2: An Asynchronous 32-bit Microprocessor Based on Scalable-Delay-Insensitive Model," Proc. IEEE Int. Conf. Computer Design, Oct. 1997, pp. 288-294.
  10. J. Garside et al., "AMULET3 Revealed," Proc. IEEE Int. Symp. Adv. Research Asynchronous Circuits Syst., Apr. 1999, pp. 51-59.
  11. A. Martin et al., "Three Generations of Asynchronous Microprocessors," IEEE Design Test Computers, Nov. 2003, pp. 9-17.
  12. M.-H. Oh and S. Kim, "Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect," ETRI J., vol. 33, no. 5, Oct. 2011, pp. 822-825. https://doi.org/10.4218/etrij.11.0211.0063
  13. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2011.
  14. Advanced Digital Chips Inc., Instruction Set Reference Manual for AE32000: a 32-bit EISC microprocessor, Nov. 2008.
  15. H. Lee, P. Beckett, and B. Appelbe, "High-Performance Extendable Instruction Set Computing," Proc. 6th ACSAC, Jan. 2001, pp. 89-94.
  16. G.N.T. Huong and S.W. Kim, "GCC2Verilog Compiler Toolset for Complete Translation of C Programming Language into Verilog HDL," ETRI J., vol. 33, no. 5, Oct. 2011, pp. 731-740. https://doi.org/10.4218/etrij.11.0110.0654
  17. S.B. Furber and P. Day, "Four-Phase Micropipeline Latch Control Circuits," IEEE Trans. Very Large Scale Integration Syst., vol. 4, no. 2, June 1996, pp. 247-253. https://doi.org/10.1109/92.502196
  18. J. Sparso and S. Furber, Principles of Asynchronous Circuit Design - A Systems Perspective, Norwell, MA: Kluwer Academic Publishers, 2001.
  19. N.C. Paver et al., "Register Locking in An Asynchronous Microprocessor," Proc. IEEE Int. Conf. Computer Design, Oct. 1992, pp. 351-355.
  20. M.R. Guthaus et al., "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," IEEE Int. Workshop Workload Characterization, Dec. 2001, pp. 3-14.
  21. R. Weicker, "Dhrystone: A Synthetic Systems Programming Benchmark," Commun. ACM, vol. 27, no. 10, Oct. 1984, pp. 1013-1030. https://doi.org/10.1145/358274.358283

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