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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder

  • Pham, Duyen Hai (School of Electronic Engineering, Soongsil University) ;
  • Moon, Jeonhak (School of Electronic Engineering, Soongsil University) ;
  • Kim, Doohwan (School of Electronic Engineering, Soongsil University) ;
  • Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
  • Received : 2014.12.15
  • Accepted : 2014.12.29
  • Published : 2014.12.31
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Abstract

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

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References

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  1. Hardware Implementation of HEVC CABAC Context Modeler vol.19, pp.2, 2015, https://doi.org/10.7471/ikeee.2015.19.2.254
  2. Design of HEVC CABAC Encoder With Parallel Processing of Bypass Bins vol.19, pp.4, 2015, https://doi.org/10.7471/ikeee.2015.19.4.583
  3. HEVC CABAC 복호화기의 역이진화기 설계 vol.20, pp.3, 2014, https://doi.org/10.7471/ikeee.2016.20.3.326
  4. HEVC CABAC 복호화기의 이진 산술 복호화기 설계 vol.20, pp.4, 2014, https://doi.org/10.7471/ikeee.2016.20.4.435
  5. HEVC CABAC 복호기의 문맥 모델러 설계 vol.21, pp.3, 2017, https://doi.org/10.7471/ikeee.2017.21.3.280