I. INTRODUCTION

Nowadays, clean and renewable energies including fuel cells, wind energy, photovoltaic, etc., have been widely applied to achieve environmentally-friendly objectives. Converters play key roles in the energy transformation [1].

As is known, a full-bridge converter can possess a higher power density by increasing the carrier frequency of the power transistors. However, the energy conversion efficiency is reduced due to the switching loss of the higher switching frequency, worsening the thermal and electromagnetic interference effects. In order to solve these problems, a phase-shift full-bridge (PSFB) converter with ZVS is proposed here. Some of the prominent features of this topology include high efficiency, high power density, and ZVS that is easy to achieve [2]. ZVS for all of the switches can be obtained by utilizing the transformer’s leakage inductance and the intrinsic capacitance of the switches without any additional circuitry [3,4]. In high power level applications, for example higher than 5 kW, insulated gate bipolar transistor (IGBT) devices are usually preferred and predominantly used as power switches [5], [6].

DC-DC converters usually utilize rectifiers at the output side. However, rectifiers having a relatively long recovery time will produce voltage spikes. The parasitic capacitance of the rectifiers will resonate with the transformer’s leakage inductance causing high frequency oscillations on the transformer’s secondary side [3].

There have been some attempts to overcome the aforementioned drawbacks. A resistance-capacitor-diode snubber circuit was proposed and it works well by limiting the peak value of the rectifier voltage oscillation [7], [8]. However, a power loss in the snubber resistance degrades the system efficiency when the output power increases.

The converter proposed in [2] employs an asymmetric auxiliary circuit to provide reactive current for the full-bridge semiconductor switches, which guarantees ZVS at the turn-on time. Although this control scheme is able to determine the optimum value of the reactive current injected by the auxiliary circuit, extra conduction losses in the power MOSFETs as well as in the auxiliary circuit can not be eliminated.

Papers [9] and [10] add auxiliary passive networks into the traditional converter and all of the primary switches can achieve ZVS in the entire load range. Furthermore, the parasitic oscillations of the rectifier voltage are lower because the leakage inductance can be designed to be rather small. However, it is a passive method not a fundamental solution for the oscillation between the leakage inductance and the parasitic capacitance of the rectifier.

In addition, there have been some improvements in the control strategy of the converter. The converter in paper [11] adopts a constant-current and constant-voltage (CC-CV) charging strategy to charge lithium-ion battery packs. To improve the transient of the voltage regulation during load variations, a Probabilistic Fuzzy Neural Network (PFNN) controller is proposed to replace the traditional PI controller and to have the ability of online learning algorithms.

A novel ZVS PSFB PWM converter is proposed here. In order to reduce the voltage oscillations and the duty cycle loss on the transformer’s secondary-side, a secondary active clamp circuit is added in this topology. The active clamp circuit consists of an IGBT, a capacitor and a diode. The voltage stress of the switches on the primary side is reduced and the ringing effect of the rectifier switches is restrained [12]. The PSFB converter realizes ZVS for the leading legs over a wide load range. The converter uses a digital signal processor (DSP) as the control core. The digital control core adopts a self adaptive PI control strategy, which provides good control performance even in harsh conditions and is simple when compared to that in paper [11]. In addition, the implementation of AD sampling and fault protection are also incorporated into the DSP [13], [14]. Experimental results are presented to verify the validity and strong points of the proposed converter.

II. OPERATION ANALYSIS OF THE CONVERTER AND ITS DIGITAL FULFILLMENT

The main topology of a PSFB converter with a secondary active clamp is shown in Fig. 1. There is a DC blocking capacitor CAB in the transformer’s primary side that is not sketched here. The converter is constructed using a full-bridge converter, a high frequency transformer T1, and a LC low-pass filter. Switches Q1-Q4 are the working switches in the full bridge. Diodes D1-D4 serve as a rectifier. The output power is controlled by adjusting the phase-shift angle φ. In the steady state, the relationship between the input voltage Vin and the output voltage Vo can be represented by the following equation:

Fig. 1.Topology of PSFB converter with secondary active clamp circuit.

Where ntr =Ns/Np is the transformer turns ratio, Np is the transformer primary turns, and Ns is the transformer secondary turns.

A. Phase-Shift Full-Bridge Operation Analyses

One working cycle of the PSFB converter can be divided into 12 operation modes (t0~t12). It is enough to analyze the first 6 operation modes since the following (7-12) modes are similar to the preceding 6 modes. The corresponding theoretical waveforms are depicted in Fig.2.

Fig. 2.Key waveforms of the PSFB converter.

1) Mode 1 (t0-t1): During this period, the IGBTs Q1 and Q4 are conducted. The transformer’s primary voltage Vab is equal to the input voltage Vin. The slope of Ip is depicted as:

2) Mode 2 (t1-t2): S1 turns off at t1 and the current Ip flows through Cs1 (the parallel buffer capacitor of Q1). Cs2 discharges when Vab gradually decreases. Both sides of the transformer are still coupled. The secondary inductor is large. Therefore, Ip remains unchanged. This mode is usually known as the leading arm transition.

3) Mode 3 (t2-t3): The intrinsic diode Ds2 (Q2’s reverse parallel diode) forward conducts and serves as a channel for Ip to flow through. During this period Q2 can turn on under zero-voltage. The current Ip is predicted as:

4) Mode 4 (t3-t4): Q4 turns off under zero-voltage at t3. The primary current Ip charges capacitor Cs4 while capacitor Cs3 gets discharged. The voltage Vab gradually decreases and drops to -Vin at t4. This negative voltage forces the secondary diodes D2 and D3 to conduct. D1 and D4 can not be shut down immediately and eventually make the transformer’s secondary short-circuited. Thus, the transformer becomes decoupled. This mode is also known as the lagging arm transition.

5) Mode 5 (t4-t5): Ds3 forward conducts at t4 and serves as a channel for Ip. Q3 can turn on under zero-voltage during this period. The current Ip is predicted as:

6) Mode 6 (t5-t6): The primary current Ip drops to zero at t5 and it flows through S2 and S3. Ip begins to grow reversely and its pace is the same as in the preceding mode. Isec also gradually increases and is equal to Io at t6. D1 and D4 turn off and both windings of the transformer regain their coupling.

B. Ringing Effect and the Secondary Active Clamp Circuit Operation Analysis

The transformer’s secondary side in a typical PSFB converter is depicted in Fig. 3. The rectifier diodes have a relatively long reverse recovery time and will cause voltage spikes when it is reversely cut-off. The voltage Vrec on the rectifier can be seen as a step voltage. Under the action of Vrec, the parasitic capacitor of the rectifier diodes Cp will resonate with the leakage inductance Llk, thus causing high frequency oscillations on the secondary side. This phenomenon is called the ringing effect [15], [16].

Fig. 3.Equivalent circuit of parasitic oscillation.

The oscillation frequency:

The defects of the voltage spike include electric stress on the components, producing EMI noise and affecting the inverter’s output characteristic. There are four commonly used measures to restrain peak oscillations [17], [18]:

An active clamp circuit is adopted here to reduce the voltage spike and ringing effect. The clamp capacitance Cs is used to resonate with the leakage inductance Llk. Cs absorbs voltage in the first half of the switching cycle and releases the energy to the load in the second half. The clamp capacitance Cs keeps its voltage unchanged in a cycle and its average charging and discharging current sums up to zero. The whole switching cycle can be seen in Fig. 4. It is advised to choose a clamp capacitance that is much larger than Llk so that the resonant period is relatively long, as well as the charging and discharging current can be restrained.

Fig. 4.Theoretical waveform of clamp circuit.

The working cycle of Qs (the secondary active clamp’s switch) is divided into 4 operation modes. The modes are analyzed as follows.

Fig. 5.Operation modes of the clamp circuit.

III. THE DIGITAL CONTROLLER DESIGN

A. Small Signal Circuit Model of a PSFB DC-DC Converter

The small-signal analysis of a PSFB converter has been carefully studied in paper [11] and paper [19]. The effective duty cycle of the transformer secondary voltage is:

Where Deff is the duty of the operating point and is the duty cycle perturbation. depends on the duty cycle d of the primary voltage as well as the filter inductor current iLO, the leakage inductance Lk, the input voltage Vdc, and the switching frequency fs. Thus, the small-signal transfer function of this converter depends on Lk, fs and the perturbations of the filter inductor current, , the dc-link voltage and the duty cycle of the primary voltage .

The small signal circuit model of a PSFB dc-dc converter is shown in Fig. 6. The contributions of and are represented by two dependent sources. Here , and Rd are represented by equation (7).

Fig. 6.Small-signal circuit model of PSFB DC-DC converter.

Thus, the open-loop transfer function is obtained as:

Where is the perturbation of the output voltage. The parameters in this transfer function are listed as follows: Vdc= 650V, Lo= 284uH, Co=75uF, ntr=11/13, Rload=30Ω, fs=20kHz, Lk=10uH, and Rd=0.573Ω. The designed PSFB converter has a phase margin of 1˚ and a bandwidth of 1847 Hz.

B. Self-Adaptive PI Controller Design

It is well known that switching DC-DC converters with parameter uncertainties and variable operating conditions are highly nonlinear systems. As a result, the conventional control method based on the averaging and linearization techniques will not provide good dynamic performance and can even make the system unstable [20], [21].

A self-adaptive PI control strategy is proposed here. The converter can work in either CC output mode or CV output mode as shown in Fig. 7 (a). When it is in CV mode, to make the output voltage quickly track the command voltage, the proportional factor Kp needs to vary in accordance with the actual output voltage. The proportional factor is defined as:

Fig. 7.Control blocks of PSFB converter. (a) Control scheme of PSFB converter. (b) Function block of voltage control. (c) Function block of current control.

Where ΔV is the difference between the expected output voltage Vr and the actual output voltage Vo . D is defined as:

The integral factor KI is then defined as:

Where k is an empirical coefficient and ranges from 3 to 30 according to the system’s properties.

When the converter works in CC mode, the same way is used to define the self adaptive PI controller. Though the proposed controller is simple and effective, it is hard to determine the empirical coefficient k which usually requires a lot of experimental testing.

C. DSP Based Controller Design

A TMS320F2812 DSP is adopted here to serve as the control core of the system. The control block consists of two self adaptive PI controllers, two limiters and a PWM generator. v*o is the output voltage command; vo is the output voltage; i*o is the output current command; io is the output current; and U’ is the limited value form the limiter. Whether the PWM generator works in CC mode or CV mode is selected by the user at startup.

For voltage control, the PI voltage controller Gc1(s) is shown in Fig.7 (b). Where is the perturbation of the output voltage command, (s) is the perturbation of the output voltage, and is the perturbation of the duty cycle for the transformer’s primary side. The open loop transfer function Tv(s) can be derived from Fig.7(b):

The same way can be used to analyze the current PI control loop and the transfer function Ti(s) can be derived from Fig.7(c):

For the required phase margin and bandwidth of the transfer function Tv(s) and Ti(s) , the compensators Gc1(s) and Gc2(s) should be carefully designed.

The DSP hardware resources are distributed as shown in Fig.8 (a). The flow charts of the main program and the two ISRs, are depicted in Fig.8 (b). The parameters and I/O initialization, the peripheral and interrupt settings and the main loop are included in the main program. The main loop deals with the procedure of self-adaptive PI control, PWM generation and the other controls in the converter. The AD interrupt service function handles the interrupt response and sampling value conversions. The AD sampling is triggered in the 25us interrupt service function, and the average values are calculated every 20 times. Then these average values are used in the self adaptive PI controller to produce the phase shift angle for the PWM generator.

Fig. 8.DSP resources distribution and program flow chats.

D. Digitally Fulfilled Phase-Shifted Control

The duty ratios of the four switches’ driving signals are 50%. The driving signals on the same arm are complementary, having a 180 degree phase lag. There is a phase lag between the leading arm and the lagging arm. The output voltage is regulated by adjusting this phase. This is the so called the phase-shifted control technique [22]-[24].

A TMS320F2812 DSP controller owns two event manager modules (EVA and EVB). T1 from EVA and T3 from EVB are applied to generate PWM for the leading and lagging arms, respectively. TXPR is used to configure the switching period, TXCMP determines the duty ratio, while TXCNT denotes the counter register values and is used to configure the phase-shifted angle.

The implementation steps include the following:

E. Digital Realization of the Secondary Active Clamp

T2 from the EVA module is used to create the PWM waveform for the clamp switch Qs.

The details are represented as follows:

IV. DESIGN CONSIDERATIONS

A. Realization of the ZVS

In order to realize ZVS in the PSFB converter, there should be enough energy to charge and discharge the paralleling capacitance in the IGBT. The criterion for ZVS is:

L is the equivalent inductance of the transformer’s primary side. Ci is the junction capacitance of the leading leg (Clead or lagging leg Clag). CT is the parasitic capacitance of the transformer’s primary winding which is usually neglected.

The achievement of ZVS in the lagging leg is not as easy as that in the leading leg. The transformer’s primary side and secondary side are coupled in the switching process as analyzed in mode 2. The inductance Lo and Llk are connected in series and the current Ip remains approximately unchanged. The criterion for the leading leg’s ZVS is:

Where td(lead) is the dead time between Q1 and Q2.

The transformer’s primary side and secondary side decouple at the lagging leg’s switching process. At this time only Llk resonate with Cs3 and Cs4. The lagging leg’s ZVS is not realized if the energy stored in Llk is not enough to charge Cs3 and Cs4. As a result, the criterion for the lagging leg’s ZVS is:

Usually equation (15) is easy to satisfy but the lagging leg’s ZVS realization needs carefully design.

B. Loss of Duty Cycle

The duty cycle on the transformer’s secondary side (Ds) is smaller than that on the primary side (Dp). In addition, Dloss is the duty cycle loss.

There are some reasons for the loss of the duty cycle: the transformer’s primary side current Ip needs time to conduct from positive to negative. During this period the transformer’s primary and secondary sides are decoupled. Dloss meets the following equation:

Time t3, t6 and t36 are expressed in Fig.2. To cope with the duty cycle loss, the saturated inductance solution is adopted here. The inductance grows to saturation when a large current flows through and exits saturation when the current drops [25].

C. Decision of Qs’s Delay Time

As shown in Fig. 1, a secondary active clamp circuit has been added to the conventional PSFB converter to restrain the voltage overshot. The driving signal of the clamp switch Qs should synchronize with the rectifier’s output voltage Vrec. Otherwise, Vrec will be affected and the peak value of Ip will increase. Considering that a PSFB converter with ZVS has a duty cycle loss on transformer’s secondary side, a Δt time-delay is needed to ensure that the clamp switch conducts before the arrival of Vrec’s rising edge. Cs has a linear charging current as shown in Fig.4. When the charging current Ic grows to zero, the voltage on the transformer’s secondary side Vrec reaches its midpoint. Therefore, it is determined that Δt meets equation (21)

Where, d means the actual duty cycle of the voltage on the transformer’s secondary side. fs means the switching frequency of the IGBTs in a PSFB converter.

V. EXPERIMENTAL RESULTS

The digital control core is a TMS320F2812 DSP. A 10kW IGBT-based prototype has been built with the parameters listed in Table I. The selections of the IGBTs and diodes are listed in Table II. The prototype is shown in Fig.9. To test the performance of the PSFB converter, a high power switching mode DC power supply, a high power resistor and a Tektronix MSO4034 oscilloscope were applied.

TABLE ICONVERTER PARAMETERS

TABLE IISELECTIONS OF KEY COMPONENTS

Fig. 9.A photo of the prototype (the converter’s PCB board is the same size as a sheet of A4 paper).

A. PSFB Converter’s Operation Properties

The driving waveforms of the converter are shown in Fig. 10. The switching frequency of the IGBTs is 20 kHz and the switching frequency of the clamp switch is 40 kHz. Fig. 11 shows the voltage and current waveforms of the transformer’s primary side. The current Ip and voltage VAB trend is the same as the theoretical waveforms.

Fig. 10.Driving waveforms.

Fig. 11.Voltage and current waveforms of transformer’s primary and secondary side.

Fig. 12 depicts the effect of the secondary active clamp circuit. When the output voltage is 40V, the voltage overshoot and ringing effect on the rectifier bridge’s output side can be seen clearly in Fig. 12(a). After adding the secondary active clamp circuit, the waveform is smooth without spikes or oscillations as shown in Fig. 12(b).

Fig. 12.Phase-shifted full-bridge converter’s output waveforms.

The converter’s output waveforms are depicted in Fig.13. The converter firstly goes into the soft start. After that it is controlled by the closed-loop self-adaptive PI controller. As can be seen from Fig.13, the soft start-up lasts for 1.6 seconds and the whole start-up period is within 2 seconds without overshoots or vibrations.

Fig. 13.The output waveforms of the converter.

The regulatory process of the conventional PI controller is about 160ms whereas that of the proposed PI controller is 97ms. The overshoot of the conventional PI controller is about 25%. However, there is hardly any overshoot with the propose PI controller. The good performance of the proposed PI controller is verified in many experiments. It has a faster respond speed, effectively suppressed vibrations and hardly any overshoot.

B. The Achievement of ZVS

Fig. 15 shows the waveforms of the ZVS. Fig. 15(a) shows the waveforms of the leading legs Q1 and Fig. 15 (b) shows the lagging leg Q3. The waveforms of Q2 resemble Q1 and are neglected here. It is the same with Q4.

Fig.14 provides the dynamic response characteristics with the proposed self-adaptive PI controller, compared to a conventional PI controller under the same conditions.

Fig. 14.Dynamic responses with 100V step voltage. ( Uin=400V DC Rload=13Ω)

Fig. 15.The waveforms of ZVS.

As can be seen in Fig.15, the time allowance for the leading legs’ zero voltage turn-on is about 500ns and for the zero voltage turn-off it is about 200ns. The prototype achieves ZVS for the leading leg successfully which helps to reduce the switching loss and improve the converter’s efficiency remarkably. The lagging leg does not achieve zero voltage turn-on because the resonant inductor Llk is small and the load is light. However, it has an 800ns time allowance for the zero voltage turn-off.

C. The Converter’s Efficiency

The efficiency of the converter has been tested and sketched in Fig.16. The input voltage Uin remained at 600V and the resistance load was 13Ω. The input current Iin was read from the DC source and the output voltage Uo was measured by a multi-meter. Finally the efficiency was calculated as:

Fig. 16.PSFB converter’s efficiency at Uin =600V & Rload =13Ω.

Fig. 16 shows an upward trend of the efficiency before 6.5kW and a downward trend after about 8kW. The lowest efficiency is 0.86 when the output power level is 0.75kW while the highest efficiency is 0.945 when power level reaches 8.2kW. The efficiency stays above 0.92 after 3kW. There is a decline in the efficiency after 8.2kW. The main reason for this may be due to the fact that the converter generates a great deal of heat.

VI. CONCLUSIONS

A digitally controlled phase-shifted full-bridge DC/DC converter using a secondary active clamp has been designed and implemented in this paper. The converter’s operation modes and the secondary active clamp circuit’s working modes have been analyzed. The features are verified by a 10-kw IGBT based prototype. Many advantages make this converter promising for high-voltage and high-power applications. Its distinctive advantages include:

There is much more to be done with this prototype such as reducing the heat produced by the converter.