DOI QR코드

DOI QR Code

EM Algorithm for Designing Soft-Decision Binary Error Correction Codes of MLC NAND Flash Memory

멀티 레벨 낸드 플래시 메모리용 연판정 복호를 수행하는 이진 ECC 설계를 위한 EM 알고리즘

  • 김성래 (한양대학교 전자컴퓨터통신공학과 부호 및 통신 연구실) ;
  • 신동준 (한양대학교 융합전자공학부)
  • Received : 2014.02.10
  • Accepted : 2014.03.03
  • Published : 2014.03.31

Abstract

In this paper, we present two signal processing techniques for designing binary error correction codes for Multi-Level Cell(MLC) NAND flash memory. MLC NAND flash memory saves the non-binary symbol at each cell and shows asymmetric channel LLR l-density which makes it difficult to design soft-decision binary error correction codes such as LDPC codes and Polar codes. Therefore, we apply density mirroring and EM algorithm for approximating the MLC NAND flash memory channel to the binary-input memoryless channel. The density mirroring processes channel LLRs to satisfy roughly all-zero codeword assumption, and then EM algorithm is applied to l-density after density mirroring for approximating it to mixture of symmetric Gaussian densities. These two signal processing techniques make it possible to use conventional code design algorithms, such as density evolution and EXIT chart, for MLC NAND flash memory channel.

멀티 레벨 낸드 플래시 메모리는 한 셀에 2 비트 이상의 정보를 저장하는 구조이고, 비트 위치별 채널 LLR의 밀도 함수 l-밀도가 비대칭 특성을 가지고 있다. 이런 특성은 이진 무기억 대칭 채널 조건에서 설계된 오류 정정부호의 성능이 제대로 발휘되지 못하게 할 뿐만 아니라, 멀티 레벨 낸드 플래시 메모리용 연판정 복호를 수행하는 이진 오류 정정 부호의 설계도 어렵게 한다. 본 논문에서 밀도 미러링과 EM 알고리즘을 이용하여 오류 정정 부호 설계를 위한 차선책을 소개한다. 밀도 미러링은 EM 알고리즘을 적용하기 전에 0 부호어를 전송한 경우로 가정할 수 있도록 하기 위해서 채널 LLR을 처리하는 과정이고, 이후 채널 LLR l-밀도를 EM 알고리즘을 적용하여 K개의 성분으로 이루어진 대칭 가우시안 혼합 밀도로 근사화하는 방법을 소개한다.

Keywords

References

  1. G. Dong, N. Xie, and T. Zhang, "On the use of soft-decision error-correction codes in NAND flash memory," IEEE Trans. Circuits and Syst., vol. 58, no. 2, pp. 429-439, Feb. 2011. https://doi.org/10.1109/TCSI.2010.2071990
  2. G. Dong, S. Li, and T. Zhang, "Using data post-compensation and pre-distortion to tolerate cell-to-cell interference in MLC NAND flash memory," IEEE Trans. Circuits and Syst., vol. 57, no. 10, pp. 2718-2728, Oct. 2010. https://doi.org/10.1109/TCSI.2010.2046966
  3. C. Yang, Y. Emre, and C. Chakrabatri, "Product code schemes for error correction in MLC NAND flash memories," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. 29, no. 12, pp. 2302-2314, Dec. 2012.
  4. H. Choi, W. Liu, and W. Sung, "VLSI implementation of BCH error correction for multilevel cell NAND flash memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 843-847, May 2010. https://doi.org/10.1109/TVLSI.2009.2015666
  5. T. J. Richardson and R. L. Urbanke, "The capacity of low-density parity-check codes under message passing decoding," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 599-618, Feb. 2001. https://doi.org/10.1109/18.910577
  6. E. Arikan, "Channel polarization : A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels," IEEE Trans. Inf. Theory, vol. 55, no. 7, pp. 3051-3073, Jul. 2009. https://doi.org/10.1109/TIT.2009.2021379
  7. S. ten Brink, "Convergence behavior of iteratively decoded parallel concatenated codes," IEEE Trans. Commun., vol. 49, pp. 1727-1737, Oct. 2001. https://doi.org/10.1109/26.957394
  8. R. Mori and T. Tanaka, "Performance and construction of polar codes on symmetric binary-input memoryless channels," in Proc. IEEE Symp. Inf. Theory, pp. 1496-1500, Seoul, South Korea, Jun. 2009.
  9. C.-C. Wang, S. R. Kulkarni, and H. V. Poor, "Density evolution for asymmetric memoryless channels," IEEE Trans. Inf. Theory, vol. 51, no. 12, pp. 4216-4236, Dec. 2005. https://doi.org/10.1109/TIT.2005.858931
  10. C. M. Bishop, Pattern Recognition and Machine Learning, Cambridge, UK: Springer, 2006.
  11. B. Lu, G. Yue, and X. Wang, "Performance analysis and design optimization of LDPC-coded MIMO OFDM systems," IEEE Trans. Signal Processing, vol. 52, no. 2, pp. 348-361, Feb. 2004. https://doi.org/10.1109/TSP.2003.820991
  12. H. G. Lee, S.-R. Kim, M.-K Lee, J.-J. Kong and D.-J. Shin, "The threshold voltage control method for mitigating cell-to-cell interference in multi-level cell NAND flash memory," in Proc. KICS Int. Conf. Commun. 2012(KICS ICC 2012), pp. 79-80, Seoul, South Korea, Nov. 2012.
  13. D. Park and J. Lee, "Performance of the coupling canceller with the various window size on the multi-level cell NAND flash memory channel," J. KICS, vol. 37A, no. 8, pp. 706-711, Aug. 2013. https://doi.org/10.7840/kics.2012.37A.8.706
  14. D. Lee and W. Sung, "Adaptive quantization scheme for multi-level cell NAND flash memory," J. KICS, vol. 38C, no. 6, pp. 540-549, Jun. 2013. https://doi.org/10.7840/kics.2013.38C.6.540
  15. S.-Y. Chung, T. J. Richardson, and R. L. Urbanke, "Analysis of sum product decoding of low-density parity-check codes using a Gaussian approximation," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 657-679, Feb. 2001. https://doi.org/10.1109/18.910580
  16. S.-Y. Chung, G. D. Forney, T. J. Richardson, and R. L. Urbanke, "On the design of low-density parity-check codes within 0.0045 dB of the shannon limit," IEEE Commun. Lett., vol. 5, pp. 58-60, Feb. 2001. https://doi.org/10.1109/4234.905935
  17. T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001. https://doi.org/10.1109/18.910578
  18. J. Hou, P. H. Siegel, L. B. Milstein, and H. D. Pfister, "Capacity-approaching bandwidthefficient coded modulation schemes based on low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 49, no. 9, pp. 2141-2155, Sep. 2003. https://doi.org/10.1109/TIT.2003.815777