Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지
DOI QR코드

DOI QR Code

Bumpless Interconnect System for Fine-pitch Devices

Fine-pitch 소자 적용을 위한 bumpless 배선 시스템

  • Received : 2014.08.07
  • Accepted : 2014.09.16
  • Published : 2014.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

차세대 전자소자는 입출력(I/O) 핀 수의 증가, 전력소모의 감소, 소형화 등으로 인해 fine-pitch 배선 시스템이 요구되고 있다. Fine-pitch 특히 10 um 이하의 fine-pitch에서는 기존의 무연솔더나 Cu pillar/solder cap 구조를 사용할 수 없기 때문에 Cu-to-Cu bumpless 배선 시스템은 2D/3D 소자 구조에서 매우 필요한 기술이라 하겠다. Bumpless 배선 기술로는 BBUL 기술, 접착제를 이용한 WOW의 본딩 기술, SAB 기술, SAM 기술, 그리고 Cu-to-Cu 열압착 본딩 기술 등이 연구되고 있다. Fine-pitch Cu-to-Cu interconnect 기술은 연결 방법에 상관없이 Cu 층의 불순물을 제거하는 표면 처리 공정, 표면 활성화, 표면 평탄도 및 거칠기가 매우 중요한 요소라 하겠다.

Keywords

References

  1. C. Lin, S. Chiang, and T. K. Yang, "Bumpless Flip Chip Packages", Int. Symp. Elcct. Mater. Packag., 173 (2002).
  2. H. Braunisch, S. Towle, R. Emery, C. Hu, and G. Vandentop, "Electrical Performance of Bumpless Build-up Layer Packaging", IEEE ECTC, 353 (2002).
  3. L. Cadix, "Flip-Chip Market and Technology Trend", Yole Development (2013).
  4. Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, and T. Suga, "Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method", IEEE Trans. Adv. Packag., 29(2), 218 (2006). https://doi.org/10.1109/TADVP.2006.873138
  5. A. Shigetou, T. Itoh, and T. Suga, "Electrical Performance and Reliability of Fine-Pitch Cu Bumpless Interconnect", IEEE ECTC, 1114 (2005).
  6. S. Towle, H. Braunisch, C. Hu, R. Emery, and G. Vandentop, "Bumpless Build-up Layer Packaging", Proc. ASME, IMECE, EPP-24703 (2001).
  7. K. Saito, T. Fujii, Y. Akiyama, T. Usami, K. Otsuka, and T. Suga, "Study on the Electrical Performance of 80 $\mu$m Pitch Bumpless Bonding for Several GHz Interconnection", IEEE ECTC 1127 (2005).
  8. T. H. Kim, M. M. R. Howlader, T. Itoh, T. Suga, "Room temperature Cu-Cu direct bonding using surface activated bonding method", J. Vac. Sci. Technol. A, 21(2), 449 (2003).
  9. W. Yang, M. Akaike, M. fujino, T. Suga, "A combined process of formic acid pretreatment for low-temperature bonding of copper electrodes", ECS SSST, 2(6), 271 (2013).
  10. C. Lin, S. Chiang, and T. K. Yang, "3D Stackable Packages with Bumpless Interconnect Technology", IEEE EPTC, 8 (2003).
  11. T. Ohba, "Bumpless WOW Stacking for Large-Scale 3D Integration", IEEE ICSICT, 70-73 (2010).
  12. D. Diehl, H. Kitada, N. Maeda, K. Fujimoto, S. Ramaswami, K. Sirajuddin, R. Yalamanchili, B. Eaton, N. Rajagopalan, R. Ding, S. Patel, Z. Cao, M. Gage, Y. Wang, W. Tu, S.W. Kim, R. Kulzer, I. Drucker, D. Erickson, T. Ritzdorf, T. Nakamura, T. Ohba, "Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology", Microelectron. Eng., 92, 3 (2012). https://doi.org/10.1016/j.mee.2011.01.082
  13. N. Maeda, H. Kitada, K. Fujimoto, Y. S. Kim, S. Kodama, S. Yoshimi, M. Akazawa, Y. Mizushima, and T. Ohba, "Development of Ultra Thin Chip-on-Wafer Process using Bumpless Interconnects for Three Dimensional Memory/ Logic Applications", IEEE VLSI Tech., 171 (2012).
  14. J. Fan, D. F. Lim, and C. S. Tan, "Effects of surface treatment on the bonding quality of wafer-level Cu-to-Cu thermo-compression bonding for 3D integration", J. Micromech. Microeng., 23, 045025 (2013). https://doi.org/10.1088/0960-1317/23/4/045025
  15. J. Lau, "Resent advances and new trend in nanotechnology and 3D integration for semiconductor industry", ESC Transactions, 44(1), 805 (2012).
  16. T. Ohba, "Wafer level three-dimensional integration (3D) using bumpless TVSV interconnects for tera-scale generation, IEEE ISCDG, 1-4 (2013).
  17. P. Enquist, "High density bond interconnect (DBI) technology for three dimenssional integrated circuit applications", Mater. Res. Sco. Sump. Proc. 970 (2007) .
  18. T. Ohba, "Bumpless through-dielectrics-silicon via technology for wafer based three-dimensional integration", ECS Transactions, 44(1), 827 (2012).
  19. C. S. Tam, L. Peng, H. Y. Li, D. F. Lin, and S. Gao, "Waferon- wafer stacking by bumpless Cu-Cu bonding and its electrical characteristics", IEEE EDL, 32(7), 943 (2011).
  20. A. Shigetou, T. Itoh, K. Sawada, and T. Suga, "Bumpless Interconnect of 6-$\mu$m pitch Cu Electrodes at Room Temperature", IEEE ECTC, 1405 (2008).
  21. C. Tan, L. Peng, J. Fan, Y. H. Li, and S. Gao, "Three-Dimensional Wafer Stacking Using Cu-Cu Bonding for Simultaneous Formation of Electrical, Mechanical, and Hermetic Bonds", IEEE Trans. Device Mater. 12, 194 (2012). https://doi.org/10.1109/TDMR.2012.2188802
  22. D. F. Lim, X. F. Ang, J. Wei, C. M. Ng, C. S. Tan, "Void density reduction at the Cu-to-Cu bonding interface by means of prebonding surface passivation with self-assembled monolayer", ECSSSL, 13(12), H412 (2010).
  23. L. Peng, H. Y. Li, D. F. Lim, S. Gao, and C. S. Tan, "High density 3D interconnect of Cu-Cu contacts with enhanced contact resistance by self-assembled monolayer (SAM) passivation", IEEE Trans. Electron Devices, 58(8), 2500-2506 (2011). https://doi.org/10.1109/TED.2011.2156415
  24. C. S. Tan, D. F. Lim, S. G. Singh, S. K. Goulet, and M. Bergkvist, "Cu-Cu diffusion bonding enhancement at low temperature by surface passivation using self-assembled monolayer of alkanethiol", Appl. Phys. Lett., 95(19), 2108 (2009).
  25. L. Peng, L. Zhang, H. Yi, G. Lo, and C. Tan, "Mechanical characterization of wafer level bump-less Cu-Cu bonding", IEEE EPTC, 437 (2012).
  26. P. Enquist, G. Fountain, C. Petteway, A. Hollingsworth, H., "Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications", IEEE 3D System Integration, 1-6 (2009).
  27. C. S. Tan, D. F. Lim, X. F. Ang, J. Wei, and K. C. Leong, "Low temperature Cu-Cu thermo-compression bonding with temporary passivation of self-assembled monolayer and its bond strength enhancement", Microelectronics Reliab., 52, 321 (2012). https://doi.org/10.1016/j.microrel.2011.04.003
  28. P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Kobrinsky, and M. Harmes, "Three-Dimensional Wafer Stacking Via Cu- Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology", IEEE Electron Device Letters, 27(5), 335 (2006). https://doi.org/10.1109/LED.2006.873424
  29. M. Park, S. E. Kim, "Study of Ar plasma treatment on Cu interconnect surface for Cu bonding in 3D integration", Proc. of MRS-K Fall, 27 (2013).
  30. J. Kim, K. Kim, H. Lee, H. Kim, Y. Park, S. Hyun, "The effect of plasma pre-cleaning on the Cu-Cu direct bonding for 3D chip stacking", IEEE IPFA, 1-4 (2011).
  31. J. Cho, S. Yu, M. Roma, S. Maganty, S. Park, E. Bersch, C. Kim and B. Sapp, "Mechanism of low-temperature copper-tocopper direct bonding for 3D TSV package interconnection", TIEEE ECTC, 1133 (2013).
  32. C. S. Tan, G. Y. Chong, "High throughput Cu-Cu bonding by non-thermo-compression method", IEEE ECTC, 1158 (2013).