I. INTRODUCTION

Non-isolated high step-up DC/DC converters are widely employed in many industrial applications, such as uninterruptable power systems, photovoltaic systems, fuel cell systems, electric vehicles, high-intensity discharge lamps, etc. [1]-[4]. Theoretically, under the ideal continuous current mode operation, the conventional boost converter can achieve a very high voltage gain with an extremely high duty cycle. However, in practice, it is difficult to design a boost converter with a very high voltage gain due to the equivalent series resistance (ESR) elements, which cause poor efficiency and a degraded voltage gain. The optimized voltage gain of the conventional boost converter is limited to approximately four times with a relative high efficiency [5], [6]. Therefore, it is not preferable for high step-up and high voltage applications.

Many isolated current-fed converters, such as current-fed push-pull converters [7], current-fed full-bridge converters [8], and dual boost converters are applied in high step-up applications [9], [10]. When compared with the voltage-fed converters, the voltage stresses of the rectifier diodes and the turns ratio of the transformer are reduced in the current-fed converters due to their boost-type configuration, which make them more suitable for obtaining a high voltage gain [11], [12]. However, at least one inductor and one transformer are required in these converters, which increases the circuit volume and reduces the power density.

When compared with an isolation transformer, a coupled inductor or tapped inductor has a simpler winding structure and lower conduction loss. Thus, a coupled-inductor-based high step-up boost converter seems to be more attractive in these high step-up applications. By introducing a coupled inductor to the conventional boost converter, the turns ratio of the coupled inductor becomes another design freedom for extending the voltage gain except for the switch duty cycle, which shows a flexibility for optimizing the efficiency and improving the utilization of the components [13]. However, the leakage inductance of the coupled inductor may cause a high voltage spike on the switch when it turns OFF. It may also induce large energy losses. In order to solve the aforementioned problems, a resistor-capacitor-diode (RCD) snubber can be employed, but the leakage energy is dissipated [14]. Passive lossless clamp circuits composed of diodes and capacitors are adopted to clamp the turn-off voltage spikes on the switch and to recycle the leakage inductance energy [15]-[18]. Thus, low-voltage rated switches can be employed to improve the efficiency. Meanwhile, the reverse-recovery problem of the output diode is partly solved by a reasonable design of the leakage inductance. However, the switches in these converters work under the hard switching condition. The active clamp circuit can be used to replace the role of the passive lossless clamp circuit. In addition, the main and clamp switches turn ON under the zero-voltage-switching (ZVS) condition, and the turn OFF losses can be greatly reduced with the help of parallel capacitors [19]. Unfortunately, the output rectifier diode suffers from very high voltage stress. Thus, high-voltage-rated diodes must be adopted, which may degrade the efficiency.

In this paper, an active clamp high step-up boost converter with a coupled inductor is proposed. Like the converter proposed in [19], the coupled inductor is included to extend the voltage ratio, while a boost type or buck-boost type clamp circuit can be employed to recycle the leakage inductance energy and achieve the zero voltage switching condition for the main and clamp switches. Moreover, a rectifier composed of a diode and a capacitor is adopted to reduce the voltage stress of the output rectifier diode. Since the voltage stresses of the switches and diodes are lower than the output voltage, low-voltage-rated metal-oxide-semiconductor field-effect transistors (MOSFETs) and diodes can be adopted for reductions of conduction losses and cost.

This paper is organized as follows. In Section II, the derivation of the proposed converter is presented and the operation analysis is described. The steady state performance analysis is carried out in Section III. Experimental results are given in Section IV, and Section V presents some conclusions drawn from the investigation.

II. DERIVATION AND OPERATION ANALYSIS OF THE CONVERTER

A. Topology Derivation

The coupled-inductor boost converter presented in [14] is shown in Fig. 1(a), and the voltage gain is given by:

Where D is the duty cycle of the main switch S and N (N=n2/n1) is the turns ratio of the coupled-inductor.

Fig. 1.The derivation of the proposed converter. (a) The coupled-inductor based boost converter presented in [14]. (b) A capacitor and a diode are added as a rectifier. (c) Active clamp circuit is included.

From (1), it is clear that a higher voltage gain than that of the conventional boost converter is achieved by introducing the coupled inductor. However, the voltage stress of the output diode Do is much higher than its output voltage when switch S is in the on state. A rectifier composed of a diode Dr and a capacitor Cr is included to reduce the voltage stress of the output diode Do as shown in Fig. 1(b). Therefore, low-voltage-rated diodes can be adopted for a reduction of the conduction losses, and a higher efficiency can be achieved than the circuit shown in Fig. 1(a). Finally, in order to make the main switch S work under the soft switching condition, a boost type active clamp circuit composed of a clamp switch Sc and a capacitor Cc is adopted, as shown in Fig. 1(c).

B. Operation Analysis

In order to perform a mode analysis of the proposed converter, several assumptions are made as follows. The coupled inductor is modeled as a magnetizing inductor Lm, a leakage inductor Llk, and an ideal transformer with a turn ratio N. Cs is the extra parallel capacitor, and the parasitic capacitors of the main and clamp switches can be included in it. Ds and Dc are the body diodes of S and Sc, respectively. The capacitors Cc, Cr and Co are large enough to assume that the voltages across them is constant. Finally, the switches and diodes are assumed to be ideal. The equivalent circuit of the converter is shown in Fig.2.

Fig. 2.The equivalent circuit of the proposed converter.

There are nine operation stages during one switching cycle. The key waveforms are shown in Fig.3 and the equivalent circuits for each stage are shown in Fig.4.

Fig. 3.Key waveforms of the proposed converter.

Fig. 4.Operational stages of the proposed converter. (a) Stage 1 [t0–t1]. (b) Stage 2 [t1–t2]. (c) Stage 3 [t2–t3]. (d) Stage 4 [t3–t4]. (e) Stage 5 [t4–t5]. (f) Stage 6 [t5–t6]. (g) Stage 7 [t6–t7]. (h) Stage 8 [t7–t8]. (i)Stage 9 [t8–t0′].

Stage 1 [t0–t1]: Before t1, the main switch S is in the ON state while the clamp switch Sc is in the OFF state. The output diode Do and rectifier diode Dr are reversed-biased. The magnetizing inductor Lm and leakage inductor Llk are connected in series and charged by the input voltage Vin. Therefore, the currents through them are equal and increase gradually in a linear way. The clamp capacitor voltage VCc and rectifier capacitor voltage VCr are unchanged. The load current is provided solely by the output capacitor Co. In this stage, the increasing rate of the magnetizing inductor current iLm and that of the leakage inductor current iLk are given by:

Stage 2 [t1–t2]: At t1, the main switch S turns off. Then, the parallel capacitor Cs is charged by the magnetizing current. Since Cs is small and Lm is relatively large, the drain-source voltage of the switch S increases and that of the clamp switch Sc decreases at a constant slope. The turn-off losses of the main switch S are reduced due to the existence of the parallel capacitor Cs. The increasing rate of the drain-source voltage vs can be derived by:

The transition interval of this stage is deduced by:

Stage 3 [t2–t3]: At t2, the drain-source voltage of the main switch S reaches the clamp voltage, and the antiparallel diode of the clamp switch Dc is forced to conduct. Therefore, vs is clamped to VCc by the antiparallel diode Dc. Since the clamp capacitor Cc is much larger than Cs, Cs can be neglected and almost all of the current flows through Cc. In this stage, the magnetizing inductor and leakage inductor are discharged by the voltage of Vin-VCc, and the currents through them decrease approximately linearly with a decreasing rate given by:

Stage 4 [t3–t4]: The turn-on signal is applied to the clamp switch Sc at t3. Sc is turned ON when its antiparallel diode Dc is conducting. Thus, the ZVS turn-on condition is achieved. The equivalent circuit in this stage is similar to that of stage 3.

Stage 5 [t4–t5]: At t4, the rectifier diode Dr and output diode Do are forced to conduct. The magnetizing inductor Lm and leakage inductor Llk are discharged by the voltages of –VCr/N and Vin+ VCr/N–VCc, respectively. Since Llk is much smaller than Lm, the decreasing rate of ilk is much greater than that of iLm. Since the output capacitor Co is relatively large when compared with the clamp capacitor Cc, the current through the output rectifier diode iDo is approximately equal to ilk. The current through the rectifier diode iDr increases linearly from zero, and the increasing rate is given by (8).

Stage 6 [t5–t6]: At t5, the current through the output diode Do decreases linearly to zero and Do turns off. The leakage inductor current iLk begins to change its direction and it increases linearly in the reverse direction. The magnetizing inductor current iLm continues to decrease linearly and the current through the rectifier diode iDr continues to increase linearly. The change rates of iLk, iLm and iDr are the same as the ones in the previous stage.

Stage 7 [t6–t7]: At t6, the clamp switch Sc turns off. The parallel capacitor Cs and the leakage inductor Llk begin to resonate. Since the resonant period is relatively large and the transition interval of this stage is relatively small too, it is reasonable to assume that the leakage inductor current iLk keeps constant and that vs decrease approximately linearly. The magnetizing inductor current iLm continues to decrease with the change rate shown in (6). The transition interval of this stage can be derived by:

Stage 8 [t7–t8]: At t7, the drain-source voltage of the main switch vs decreases to zero and the parallel diode Ds is forced to conduct. The voltage across the leakage inductor is equal to Vin+VCr/N, and the change rate is derived by (10). The magnetizing inductor current iLm continues to decrease in this stage.

Stage 9 [t8–t0′]: At t8, the turn-on signal is applied to the main switch S when its antiparallel diode is in the ON state. Therefore, the main switch S turns ON with ZVS. The equivalent circuit of this stage is similar to that of the previous stage. At t0′, the leakage inductor current iLk increases to be equal to the magnetizing inductor current iLm, the current through the rectifier diode iDr drops to zero, and Dr turns off. After that, the magnetizing inductor Lm and leakage inductor Llk are connected in series and charged by the input voltage Vin again. Then, a new switching period begins.

III. STEADY STATE PERFORMANCE ANALYSIS

A. Voltage Gain

When the leakage inductor LLk is equal to zero, one switching cycle can be separated into two stages. When the main switch S is in the ON state and the clamp switch Sc is in the OFF state, the voltage across the magnetizing inductor Lm, VLm-charge can be derived by:

When the main switch S is in the OFF state and the clamp switch Sc is in the ON state, the magnetizing inductor is discharged by VLm-discharge, and VLm-discharge is deduced by:

By applying the inductor volt-second balance principle to the magnetizing inductor, the voltage across the clamp capacitor VCc can be derived by:

Since the magnetizing inductor current iLm is continuous, the capacitor voltage VCr can de deduced by:

Apparently, the output voltage Vo is the sum of VCc and VCr. Therefore, the ideal voltage gain Mideal when the leakage inductor is omitted can be obtain by:

From the operation analysis in Section II, it can be seen that the leakage inductor Llk causes little duty cycle loss. The voltage gain when considering the influence of leakage inductor Llk is deduced as follows.

Since the time intervals from t1 to t4 and from t6 to t8 are relatively short when compared with the switching cycle, they are excluded in the following voltage gain analysis, and there are only four stages during one switching cycle. The ideal current waveform of the leakage inductance is taken as a straight line during each subinterval due to the relatively large resonant period. Simplified waveforms are shown in Fig. 5.

Fig. 5.The simplified waveforms.

During the time interval from t0 to t4, the main switch S is in the ON state and the clamp switch Sc is in the OFF state. Moreover, the rectifier diode Dr is reverse biased. The magnetizing inductor Lm and leakage inductor Llk are series connected and charged by VLm-charge and VLlk-charge, respectively. VLm-charge and VLlk-charge are derived by:

During the time interval from t4 to t6, the main switch S is in the OFF state and the clamp switch Sc is in the ON state. At the same time, the rectifier diode Dr is forced to conduct. The magnetizing inductor Lm and leakage inductor Llk are discharged by VLm-discharge and VLlk-discharge, respectively, and can be obtained by:

During the last time interval in one switching cycle from t6 to t0′, the main switch S is in the ON state and the clamp switch Sc is in the OFF state. In addition, the rectifier diode Dr is forward biased in this time interval. The magnetizing inductor is discharged by VLm-discharge which can be obtained by (18), while the leakage inductor is charged by VLlk-charge which can be derived by:

By applying the volt-second balance principle to the magnetizing inductor Lm and leakage inductor Llk, the following equations can be derived:

At t6, the current through the diode Df, iDr reaches its peak value IDr-peak which can be deduced by (23), and the average value of iDr, IDf can be obtained by (24):

When operating at the steady state, the average currents through the capacitors Cr and Co are zero. Therefore, IDr should be equal to the output current Io and the following equation is obtained:

Apparently, the output voltage Vo is the sum of VCc and VCr, that is:

From (21), (22) and (24) to (26), the voltage gain of the proposed converter, when considering the leakage inductor, can be expressed by:

Where kL=Llk/Lm and km=Llkfs/Ro. fs is the switching frequency.

The relationship between the voltage gain, the duty cycle, the leakage inductor, and the turns ratio with Lm=120 μH, fs=100 kHz, Ro=578 Ω is shown in Fig. 6. It is concluded that the voltage gain ratio increases significantly as the turns ratio of the coupled inductor increases, which is a desirable feature in high step-up high efficiency applications because a very narrow turn-OFF period is avoided. When the turns ratio is zero, the voltage gain of the proposed converter is the same as that of the conventional boost converter. The leakage inductor has little effect on the voltage gain of the converter. As the leakage inductor increases, the voltage gain decreases.

Fig. 6.The voltage gain of the proposed converter.

B. Voltage and Current Stresses

Neglecting the voltage ripples on the capacitors Cc, Cr and Co, and assuming the leakage inductor to be zero, the voltage stress of the main switch S, VS-stress is equal to the voltage stress of the clamp switch Sc, VSc-stress, which can be derived by:

The voltage stress of the rectifier diode Dr, VDr-stress is given by:

From (14) and (29), VDr-stress is obtained by:

The voltage stress of the output diode Do, VDo-stress is given by:

From (14), (15) and (31), VDo-stress is obtained by:

From (15), (28) and (32), VS-stress, VSc-stress, and VDo-stress are equivalent and they are lower than the output voltage Vo. Fig. 7(a) shows the voltage stress normalized by Vo. When the duty cycle D and the turns ratio N increase, the voltage stress decreases. Since VS-stress and VSc-stress are much lower than the output voltage Vo, low-voltage-rated switches can be used to improve the efficiency. From (15) and (30), the voltage stress of the rectifier diode Dr VDr-stress normalized by the output voltage Vo is shown in Fig. 7(b). It can be seen that the voltage stress on Dr decreases as the duty cycle D increases or as the turns ratio N decreases. Moreover, it is lower than the output voltage Vo if the following condition is satisfied:

Fig. 7.The voltage stresses according to the variation of duty cycle D and turns ratio N. (a) VS-stress, VSc-stress, VDo-stress normalized by Vo. (b) VDr-stress normalized by Vo.

According to the operation analysis of the proposed converter in Section II, the current stresses of the main switch S, the clamp switch Sc, and the output diode Do, which are expressed by IS-stress, ISc-stress, and IDo-stress, respectively, are similarly equal to the peak value of the current through the output rectifier diode Do, IDo-peak. From Fig.5, IDo-peak can be deduced by:

Since the average value of the current through the output rectifier diode Do, IDo should be equal to the output current Io when operating at the steady state, the following equation is obtained:

Additionally, the clamp capacitor voltage VCc is given by:

From (26), (27) and (34) to (36), D1 can be derived by:

Therefore, IS-stress, ISc-stress and IDo-stress can be deduced by:

IS-stress, ISc-stress and IDo-stress normalized by Io according to variations of the duty cycle D, the turns ratio N and the leakage inductor Llk are shown in Fig. 8(a). It is shown that the current stress increases with an increasing duty cycle D. Additionally, as the turns ratio N decreases and the leakage inductor Llk increases, the current stress decreases.

Fig. 8.The current stress of the main switch S, clamp switch Sc, output diode Do, and rectifier diode Dr normalized by Io. (a) IS-stress, ISc-stress, IDo-stress normalized by Io. (b) IDr-stress normalized by Io with N=4. (c) IDr-stress normalized by Io with N=2. (d) IDr-stress normalized by Io with N=1.

From (23), (26), (27) and (32), the current stress of the rectifier diode Dr, IDr-stress can be derived by:

IDr-stress normalized by Io according to variations of the duty cycle D, the turns ratio N and the leakage inductor Llk is shown in Fig. 8(b) to Fig. 8(d) with N=4, N=2, and N=1 respectively for clear. It is show that the current stress of the rectifier diode Dr increases with an increasing duty cycle. However, it decreases with an increasing leakage inductor. Moreover, from Fig. 8(b) to Fig. 8(d), the current stress IDr-stress increases with a decreasing turns ratio N.

C. Soft Switching Condition

The turn-off losses of the main and clamp switches are reduced because of the parallel capacitor. The reverse-recovery losses of the diodes are negligible since the leakage inductor provides a current snubbing effect. The ZVS turn-on condition of the clamp switch can be realized by applying a turn-on signal when its antiparallel diode is in the ON state and the drain-source voltage is clamped to zero. To realize to the ZVS turn-on condition of the main switch, the energy stored in the leakage inductor should be greater than that stored in the parallel capacitor when the clamp switch turns off. Therefore, the ZVS turn-on condition of the main switch can be derived by:

IV. EXPERIMENTAL RESULTS AND ANALYSIS

In order to verify the performance of the proposed converter, a 250W prototype is built and tested. Due to the resonance between the leakage inductor of the coupled inductor and the junction capacitor of the rectifier diode Dr, it is necessary to add a proper resistor-capacitor-diode (RCD) snubber to reduce the voltage spike across Dr, as shown in Fig. 9. Since the current level at the high-voltage side of the coupled inductor is relatively low, even though an RCD snubber is adopted, the conversion efficiency will not drop significantly. The parameters of the converter are described in Table I and the experimental results of the proposed converter are shown in Fig. 10.

Fig. 9.The proposed converter with RCD snubber.

TABLE IPARAMETER OF THE PROTOTYPE

Fig.10.The experimental results of the proposed converter. (a) The measured waveforms of QS, Vin and Vo. (b) Leakage current iLk and magnetizing inductance voltage vLm (c) ZVS-on performance of main switch S. (d) ZVS-on performance of clamp switch Sc. (e) Voltage and current waveforms of rectifier diode Dr and output diode Do.

Fig. 10(a) shows the gate-source voltage of the main switch QS, the input voltage Vin and the output voltage Vo. The measured duty cycle is about 0.68 as predicted by (15), and high step-up capacity is verified. The current of the leakage inductance iLk and the voltage of the magnetizing inductance vLm are shown in Fig. 10(b). It can be seen that the experimental results are consistent with the theoretical analysis. The gate-source voltage, drain-source voltage and current experimental waveforms of the main switch S and the clamp switch Sc are shown in Fig. 10(c) and Fig. 10(d) respectively. It is shown that both the main switch and the clamp switch are turned ON and OFF under the ZVS condition. This reduces the switching losses greatly. Moreover, the voltage stresses of the main switch and clamp switch is about 160V. Thus, low-voltage-rated MOSFETs can be adopted and the conduction losses can be reduced. Fig. 10(e) shows voltage and current waveforms of the rectifier diode Dr and the output rectifier diode Do. Clearly, the reverse-recovery current of the rectifier diode Dr and output rectifier diode Do is small because the reverse-recovery problem is alleviated by the leakage inductance of the coupled inductor. As a result, the reverse-recovery losses are minimized. The voltage waveform of the output diode in the converter proposed in [19] is illustrated in Fig. 11. It shows that the voltage stress of the diode is 550V, which is much higher than the 380V of the rectifier diode Dr and the 160V of the output rectifier diode Do in the proposed converter. Therefore, a low forward voltage drop diode can be used to improve the efficiency of the proposed converter. An efficiency comparison between the proposed converter and the converter proposed in reference [19] is plotted in Fig. 12. It can be seen that the maximum efficiency of the proposed converter is 95% with a 48V input and a 380V output conversion when operating at 100kHz. When compared with the converter proposed in reference [19], there is about a 1% efficiency improvement under full load and about a 3% efficiency improvement under light load.

Fig. 11.Voltage waveforms of output diode in the converter proposed in [19].

Fig. 12.The efficiency comparison between proposed converter and converter proposed in reference [19].

V. CONCLUSIONS

An active clamp high step-up boost converter with a coupled inductor has been proposed in this paper. A coupled inductor is included to extent the voltage gain. By applying an active clamp circuit, the main and clamp switches operate under the ZVS condition and the switching losses are minimized. The reverse-recovery problems of the diodes are solved due to the inherent leakage inductor of the coupled inductor. Additionally, the voltage stress of the output diode is reduced by adopting a rectifier composed of a diode and a capacitor. The derivation of the proposed converter is presented. A steady-state operational analysis and the main circuit performance are discussed to explore the advantages of the proposed converter. Finally, a 250W prototype has been built and experimental results have been presented to verify the analysis.