Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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A Study on the Parameters of Design for Warpage reduction of Passive components Embedded Substrate for PoP

PoP용 패시브 소자 임베디드 기판의 warpage 감소를 위한 파라메타 설계에 관한 연구

  • Received : 2015.02.26
  • Accepted : 2015.03.24
  • Published : 2015.03.30
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Abstract

In this paper, numerical analysis by finite element method and parameter design by the Taguchi method were used to reduce warpage of a two passive components embedded double side substrate for PoP(Package on Package). The effect of thickness of circuit layers (L1, L2) and thickness of solder resist (SR_top, SR_BTM) were analyzed with 4 variations and 3 levels(minimum, average and maximum thickness) to find optimized thickness conditions. Also, paste effect of solder resist on unit area of top surface was analyzed. Finally, experiments was carried out to prove numerical analysis and the Taguchi method. Based on the numerical and experimental results, it was known that circuit layer in ball side of substrate was the most severe determining deviation for reducing warpage. Buried circuit layer in chip side, solder resist and were insignificant effects on warpage relatively. However, warpage decreased as circuit layer in ball side thickness increased but effect of solder resist and circuit layer in chip side thickness were conversely.

본 논문에서는 2개의 패시브 소자가 임베디드된 PoP(Package on Package)용 양면 기판의 휨을 감소시키기 위해 유한요소법을 이용한 수치해석과 파라메타 설계를 위한 다구찌법이 사용되었다. 양면 회로층 두께와 솔더 레지스트 두께가 4인자 3수준으로 설계되어 파라메타 영향도가 분석되었다. 또한, 유닛 영역의 솔더 레지스트가 제거하거나 도포된 모델의 휨을 해석하여 솔더 레지스트의 영향도를 분석하였다. 마지막으로 실험을 통해 수치해석과 다구찌법에 의한 파라메타 설계의 효과를 입증하였다. 연구결과에 의하면 휨에 미치는 영향은 볼 사이드에 있는 회로층이 지배적으로 크고 칩 사이드의 회로층이 두 번째로 크며 솔더 레지스트의 영향이 가장 작았다. 또한, 칩 사이드 유닛영역의 솔더 레지스트는 도포 유무에 따른 영향도가 매우 작았다. 한편 기판의 휨은 볼 사이드 회로층의 두께가 얇을수록, 칩 사이드 회로층의 두께와 솔더 레지스트의 두께는 두꺼울수록 감소하였다.

Keywords

References

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