I. INTRODUCTION

Recently, photovoltaic (PV) power systems has become an attractive candidate due to the increases in energy demand and the concern over environmental pollution around the world. Various kinds of configurations are being developed in grid-connected systems. Generally, a system can be employed as a small-scale distributed generation (DG) system, where the most important design constraint of the PV DG system is to obtain a high voltage gain. For a typical PV module, the open-circuit voltage is about 21~28 V [1], [2]. However, the public DC bus voltage is usually set to 200V or 400V [3], [4]. Therefore, a high step-up dc-dc converter with a high voltage conversion ratio, a low input-current ripple, a low output-voltage ripple and a high efficiency is required to realize the grid-connected function and to achieve a low total harmonic distortion (THD).

Until now, various current-fed step-up conversion topologies have been proposed in photovoltaic (PV) power systems [6]-[10]. These topologies have desirable advantages such as a high voltage conversion ratio, a low input current ripple, a high power capability and galvanic isolation between the input and output sides. However, they have a common serious problem caused by the leakage inductance of the transformer. It is well known that converters with a power transformer suffer high voltage surges across the switches in current-fed topologies such as the current-fed push-pull converter, current-fed full-bridge converter and current-fed half bridge converter. Thus, a snubber circuit is required to absorb the surge energy to protect the switching devices from a permanent breakdown. Moreover, in current-fed power conversion topologies, the snubber circuit has to accommodate the entire boost current until the transformer leakage inductor current is built up to the level of the boost inductor current. Hence, a well-designed snubber circuit is essential for solving these problems. However this greatly increases the circuit design complexity and cost. Most importantly, because the rectifier diodes are turned off at hard switching, the exiting reverse-recovery problem will shade the efficiency improvement [11]-[14].

Many voltage-fed converters have also been proposed with step-up dc-dc topologies for high gain [15]-[19]. However, these voltage-fed converters may not be optimal due to a large input current ripple, which is not beneficial for MPPT control. Reducing the input current ripple in a voltage-fed converter requires an additional LC filter across the photovoltaic cell stack, which lowers the power efficiency. Additionally, a high frequency transformer with a high turns ratio is required, which increases the voltage stress on the primary elements, and imposes a heavy penalty on the efficiency. As with the current-fed topologies, the reverse-recovery problem is not solved.

Based on those considerations, some resonant converters have been proposed [20]-[22]. However, some disadvantages prevent their popularity. Even the dual resonant circuit applications in [20], [21] produce a double output voltage, and two windings are required for the transformer which results in design complexity and a bottleneck for power density. The authors of [22] provide an ingenious method to achieve a high step-up through a resonant circuit. Unfortunately, the primary inverter bridge fails to realize the soft switching and a transformer with a high turns-ratio is required. Recently, a novel class of resonant converters including the serial resonant converter (SRC), parallel resonant converter (PRC) and series parallel resonant converter (SPRC, also known as an LCC resonant converter) has been developed [23]-[25]. By adjusting the frequency, these resonant circuits can realize ZCS for all of the rectifier diodes, and voltage/current spikes can be suppressed in the primary switches due to a sinusoidal current though the switches instead of a square current. In addition, these circuits enjoy a relative high efficiency. However, some drawbacks limit their wide application:

To solve above problems mentioned, a novel isolated converter with an input current doubler, a resonant switched-capacitor circuit and an active-clamp circuit is proposed in this paper. The operation of the proposed converter is analyzed in section II, and the control scheme is described in section III. Then, the performance is discussed in section IV. Finally, some experimental results and waveforms are presented to verify the performance of the proposed converter in section V.

II. PROPOSED CONVERTER AND OPERATION PRINCIPLE

The proposed converter and its simplified circuit model are shown in Fig. 1. It is composed of a current doubler and a switched-capacitor circuit. The current doubler circuit is plotted in the left dashed block of Fig. 1. Two out-of-phase pulses with an adjustable width are supplied to drive the main switches S2 and S4. The auxiliary switches S1, S3 are driven complementarily by the main switches S2, S4, respectively. The inductors L1, L2 are connected to the main switches S2, S4, respectively. The active-clamp circuit is composed of the clamp capacitor Cc and the auxiliary switches S1, S3. The switched-capacitor circuit is plotted in the right dashed block of Fig. 1, which is composed of the rectifier diodes D1, D2, D3, D4 and the capacitors C1a, C1b, C2a, C2b. This circuit provides two complementary series-resonant loops to achieve the ZCS turn-off for all the rectifier diodes. One loop is the transformer leakage inductance Llk resonating with C1a, and the other loop is the transformer leakage inductance Llk resonating with C1b.

Fig. 1.Proposed converter and its equivalent circuit. (a) Proposed converter. (b) Simplified circuit model. (c) Voltage-level-extension topology with N SC blocks.

By adding a different number of the SC blocks, which functions as a rectifier, as shown in the dotted box in Fig.1(c), the voltage-level-extension topology can be obtained. For every block that is added to the converter, 4 times νs will be added to the output voltage, where 4 diodes and 4 capacitors are utilized. Assume that the various rectifiers output the same power and the same voltage. The voltage on the primary-winding of the transformer is Vp, the output voltage is Vo and Vo=4Vp, and output current is Io. A performance comparison between the SC rectifier and conventional rectifiers (a full bridge rectifier and a full wave rectifier) is shown in Table I.

TABLE IPERFORMANCE COMPARISON BETWEEN SC RECTIFIER AND CONVENTIONAL RECTIFIERS

From Table I, it can be concluded that the proposed SC rectifier benefits in terms of the turn ration of the transformer when compared with conventional rectifiers. Meanwhile, lower voltage stress of the diodes, soft switching realization for the diodes and less output voltage ripple make the proposed SC rectifier a better candidate for rectification.

To analyze the stead-state operation of the proposed converter, several assumptions are made during one switching period Ts.

The steady-state operation of the proposed converter during one switching period Ts can be divided into ten stages. The equivalent circuits and the key waveforms in each operation stage are described in Fig. 2 and Fig. 3, respectively.

Fig. 2.Operation stages of the proposed converter. (a) Stage 1. (b) Stage 2. (c) Stage 3. (d) Stage 4. (e) Stage 5. (f) Stage 6. (g) Stage 7. (h) Stage 8. (i) Stage 9. (j) Stage 10.

Fig. 3.Key waveforms of the proposed converter.

Stage 1 [t0, t1]: At t0, S4 is turned on. Then, the inductor current iL1 flows through S4, and the inductor current iL2 flows through S2. Since both of the main switches S2, S4 are in the on-state, the primary voltage νp of the transformer is zero. In addition, both the primary current of the transformer ip and the secondary current of the transformer is are zero. Then, the inductor currents iL1, iL2 increase linearly as follows:

Where, Vin is the output voltage of a photovoltaic battery.

Stage 2 [t1, t2]: At t1, S2 is turned off. iL2 begins to discharge Cs1 and charge Cs2 linearly. After iL2 fully charges Cs2 to VCc, and Cs1 discharges to 0 V, it flows through the anti-parallel diode of the switch S1. Therefore, the zero voltage across S1 is maintained, and the switch S1 can be turned on at ZVS in the next stage.

During this stage, the input power is transferred to the output side. Since the voltage across the primary winding of the transformer is νp =-VCc, the secondary winding voltage is:

Where, the turns ratio N of the transformer is given by N2/N1. There are two resonant loops. One is the leakage inductor Llk, C1a, D1 and the other one is Llk, C1b, D4, C2b. The resonant capacitors C1a is charged by νs. At the same time, νs and C1b in series charge C2b. Both D1, D4 conduct. The state equations can be written as follows:

Here, is, νC1a and νC1b are obtained as follows:

Where, Is,peak is the peak current of the secondary transformer. The angular frequency ωr and the resonant impedance Zr are given by:

iCc can be easily obtained as:

Stage 3 [t2, t3]: At t2, S1 is turned on while its body diode conducts. Hence, the switch S1 is turned-on at the ZVS condition. iL1 increases continuously as in (1), and iL2 decreases linearly as follows:

The two resonance-loops (νs, Lk, D1, C1a and νs, Lk, C1b, D4, C2b) continue to resonate. In addition, ip, iCc, is, νC1a, νC1b satisfy (6) (7) (8) (10) (11).

Stage 4 [t3, t4]: At t3, the currents iD1, iD4 of the diodes D1, D4 become zero, and ip decreases to zero. In addition, iL1 still increases linearly and iL2 still decreases linearly, as shown in Fig. 3. Furthermore, the anti-parallel diode of the switch S1 conducts again. Since the resonance of the two loops is terminated at t3, the diodes D1, D4 are turned off at ZCS, whose reverse-recovery problem has been removed.

Stage 5 [t4, t5]: At t4, the anti-parallel diode of S1 begins to conduct. Hence, the switch S1 is turned off at ZVS.

Stage 6 [t5, t6]: At t5, S2 is turned on. This stage is analogous to stage 1. Therefore, the analysis of this stage is omitted.

Stage 7 [t6, t7]: At t6, S4 is turned off. In addition, iL1 begins to charge Cs3 and discharge Cs4 linearly. After iL1 fully charges Cs4 to VCc and discharges Cs3 to 0 V, it flows through the anti-parallel diode of the switch S3. Therefore, the zero voltage across the switch S3 is maintained, and the switch S3 can be turned on at ZVS in the next stage.

Like stage 2, during this stage, the input power is transferred to the output side. Since the voltage across the primary winding of the transformer is νp = VCc, the secondary winding voltage is:

There are two resonant loops. One loop is formed by C1a, D3, C2a, Llk. C1a and νs. It charges C2a in series. The other loop is formed by C1b, D2, Llk and νs. C1b is charged by νs. Since the output capacitors C2a, C2b are sufficiently large when compared to the resonant capacitors C1a, C1b, the capacitors of the two resonant loops can be equivalent as C1a, C1b, respectively. The state equations can be written as follows:

Here, C1a is equal to C1, and C1b is the same as C1a.

Consequently, νC1a and νC1b can be derived as:

Stage 8 [t7, t8]: At t7, S3 is turned on while its body diode has conducted. Hence, S3 is turned on at ZVS. iL2 increases continuously as (2), and iL1 decreases linearly as follows:

Stage 9 [t8, t9]: Similar to stage 4, the diodes D2, D3 are turned off at ZCS. There is no reverse-recovery problem for the diodes D2, D3. The anti-parallel diode of the switch S3 begins to conduct. The output current Io is:

By combining (18) and (20), Is,peak is obtained as:

Stage 10 [t9, t10]: At t9, switch S3 is turned off at ZVS. Similar operation stages work in the rest of the stages in a switching period.

In the operation analysis discussed above, the duty cycle D is more than 0.5. When D is less than 0.5, the operation analysis is similar but the switching sequence is different. The switching sequences of two cases are summarized in Table II.

TABLE IISWITCHING SEQUENCE AT DIFFERENT DUTY CYCLE

It should be pointed out that the bottom switches S2, S4 cannot achieve ZVS turn-on in this topology. However, this issue can be solved by adding an auxiliary circuit. The boundary condition will be derived and discussed in future works due to page limitations.

An operation analysis of the switched-capacitor doubler is discussed in Appendix A.

III. THE CONTROL SCHEME OF THE PROPOSED CONVERTER

Pulse-width modulation plus phase angle shift (PPAS) is used as the control scheme in the proposed converter. The current doubler port is plotted in Fig. 4(a). An interleaved boost converter is employed in the current doubler port shown in Fig. 4(a), which is the front part of the proposed converter shown in the left dashed block in Fig. 1(a). Where, Vbus is equal to VCc, νp is the phase voltage difference between the leg BB1 and the leg BB2. Steady-state waveforms of the control scheme are described in Fig. 4(b). Where, D is duty cycle of the switches S2 and S4, and Ts is the switching period. It is noted that the phase angle between BB1 and BB2 is kept at a constant 180° to reduce the current ripple. D is employed as the only control freedom to achieve output voltage regulation. Once D is adjusted during a selected range, the phase voltage difference νp will vary correspondingly, as shown in Fig. 4(b). Hence, the transformer can be inserted into the primary side (point A and point B) and the switched-capacitor circuit (point C and point D), as shown in Fig. 1, to realize output voltage regulation. The relationship between the duty cycle, the transformer turns ratio N and the voltage conversion is derived in the next section.

Fig. 4.Control scheme of the proposed converter. (a) Current doubler port. (b) Key steady-state waveforms.

IV. PERFORMANCE ANALYSIS AND DESIGN CONSIDERATIONS OF THE CONVERTER

A. Voltage Gain Ratio

The volt-second balance law of L1 during one switching period determines the relation between Vin and VCc as follows:

Then, formula (22) can be derived as:

The volt-second balance law of Llk during one switching period provides the following relationship between the resonant capacitor average voltage Vc1a and Vo:

Where, To is the resonant period. Hence, the average voltage of the resonant capacitor Vc1a is obtained as:

Due to symmetry, Vc1b is equal to Vc1a.

The average value Vc1a is equal to the amplitude of νs, and the amplitude of νp is equal to VCc. Therefore, the relationship between the clamp capacitor voltage and the output voltage can be written as:

By combining (22) and (26), the relationship between the input voltage Vin and the output voltage Vo can be derived as:

B. Resonant Capacitor

The existence of stage 3 and stage 8 ensures the ZCS turn-off for the rectifier diodes D1,D2,D3, D4. The interval of stage 3 and stage 8 changes with variations of resonant frequency and duty ratio. To achieve ZCS turn-off for all of the rectifier diodes D1, D4, D2, and D3, the following critical conditions must be satisfied:

Where, ωr is the critical angular resonant frequency. Therefore, the resonant capacitor C1a must meet the following relationship:

The leak inductance is an inductive reactance by nature. If the leak inductance is too large, the output capability of the system will be influenced. Of course, this also influences the switching frequency, current and voltage stress of the resonant elements since it participants the resonance process. In practical transformer design, it is difficult for the real value of the leakage inductance to meet the theoretical value well and there is some deviation. Therefore, the switching frequency and the resonant capacitor are determined based on the leak inductance, which means that the switching frequency and resonant capacitor values will be adjusted with deviations of the leak inductance.

C. Input Current Ripple

Assuming that the boost inductors L1 and L2 have the same value L, the input-current ripple ΔIin of the photovoltaic cell is:

The maximum input current ripple ΔIin,max occurs at the duty ratio D= 2/3. The maximum input current ripple ΔIin,max is:

The current ripple of L1 and L2 is:

The maximum current ripple at the duty ratio D=0.5 is:

From (31) and (33), the maximum input current ripple is much less than that of iL1 and iL2.

D. Topology Extension of the Proposed Converter

The proposed converter, composed of a current doubler and a quasi-resonant switched-capacitor circuit, can be extended to other converters. The first one is the extension on the primary port as shown in the left dashed block of Fig. 5(a)-5(c), and the second one is the extension on the secondary port as show in the right dashed block of Fig. 5(a)-5(c).

Fig. 5.Extension of the proposed converter (a) Type I(b) Type II(c) Type III

The current doubler is extended into the three types shown in Fig. 5(a)-(c). The primary port of type I is an interleaved buck-boost converter. Unlike the proposed converter, the clamp capacitor is connected to the positive of the power source so that it can endure the lower voltage stresses of the clamp capacitor. However, a larger capacitance is required. Similarly, the primary port of type II is an interleaved buck-boost converter. However, the upper switches S1, S3 are employed as main switches and Vin is float. On the other hand, the primary port of type III is a current-fed half bridge converter. The current-fed DC-DC isolated converters, use fewer switches without an active clamp circuit.

The switched-capacitor circuit can be extended to attain a different voltage gain by adding or removing switched-capacitor cells as shown in the green block of Fig. 5(a)-(c). In Fig. 5(a)-(c), there are two switched-capacitor cells and 8 times the voltage of the transformer secondary winding can be reached in the output port. A general principle is that M switched-capacitor cells are employed and 4M times the voltage is obtained through the switched-capacitor circuit.

E. Performance Comparison

For conventional current-fed full-bridge converters [28], to provide a current path for the input inductor, the duty cycle of the primary main switches should be greater than 0.5 under any load condition. Consequently, an additional start-up circuit should be designed to minimize the inrush current during the start-up process. Meanwhile, the primary current should flow through two primary switches in most of the operation states, which results in large switch conduction losses. In addition, the current stress of the input inductor is high due to its whole input current maintenance. Last, the magnetizing currents of the two inductors cannot be limited since this leads to a minimum output power level. However, the main-switch duty cycle of the proposed converter can vary from 0 to 1. When the duty cycle is lower than 0.5, the present converter may work in the discontinuous current mode with a light load. As a result, the ZVS performance is lost because the leakage energy is not sufficient to discharge the energy stored in the parallel capacitor when the corresponding clamp switch turns off. In addition, a wide duty-cycle operation range is achieved in the proposed converter to remove the additional start-up circuit. Moreover, the current stress of the magnetizing inductors is decreased because of the large input current distribution in the two interleaved phases. Finally, the primary switch conduction loss is reduced. This is because the primary current only flows through one switch and the average current stress on the active-clamp switches is relatively low. In other words, the proposed converter is more suitable for high-efficiency, high step-up, and high-power-density dc/dc conversions when compared with the conventional current-fed full-bridge converters.

The authors of [29] presented a topology that is similar to the proposed converter except for the reduced clamped-capacitor utilized in primary-side of the proposed converter. The main difference is the control strategy. This results in different operation principles for the two converters. They have some similar merits, such as soft switching realization for primary-side MOSFET switches and secondary-side diodes, few turn ration of the transformer, and a low output-voltage ripple. Due to the sawtooth-wave current through the switches and diodes for the converter in [29], there is higher peak current when compared with the sine-wave current operation of the proposed converter at the same average output current. This means higher conduction losses in primary-side switches and in the secondary-side diodes for the converter in [29].

A more detailed comparison between the conventional current-fed full bridge converter, the converter in [29] and the proposed converter is summarized in Table III. Assume that the three converters have the same power rating and voltage gain. Define Vin, Iin, Uo, Io, and D as the input voltage, input current, output voltage, output current and duty cycle, respectively. Introduce the concept of DPTR (device power total rating, which is equal to the current rating times the voltage rating) to descript the device cost.

TABLE IIIPERFORMANCE COMPARISON

F. Design Consideration

The 400-W design procedure of the proposed converter is shown here as an example. Some of the specifications of the prototype converter are set first: Vin =25V, Vo= 200 V, Po= 400 W, N1/N2=18:18, Lk=1uH, and fs=50 kHz.

1) Resonant Frequency: In order to provide ZCS turn-off for the rectifier diodes D1, D2, D3, D4, in addition to making sure the switching frequency is lower than the resonant frequency, other relations need to be satisfied:

Where, To is resonant period. Here, set fo=80KHz.

2) Resonant Capacitor: The resonant capacitance value should meet (29), and it should be chosen according to the voltage ripple[26][27]. A detailed derivation is discussed in Appendix A:

Where, C1 is resonant capacitor value. The value of the voltage ripple is determined by the output current, the resonant capacitance value and the switching frequency. The capacitor voltage ripple should be smaller than the average voltage (equal to vs) to prevent voltage across the resonant capacitor from the positive to negative region and losing ZCS. This means that the resonant capacitor should have a positive dc voltage offset.

3) Output Capacitor: Another consideration is that the maximum voltage ripple should be less than one third of the dc component. Here, a 20% voltage ripple is considered for the resonant capacitor. Then the resonant capacitance value can be derived as:

Here, a 2uF resonant capacitor is selected.

C2 is large enough to maintain a constant voltage for each stage.

Where, θ=sin-1(fs)/(πfo) and Io = (Po)/(Vo) .

For a 0.1 V ripple voltage, this gives C2=59.2uF and 47uF is selected.

4) Duty Cycle: According to (34), the duty cycle range is selected to be 0.3375

5) Other Considerations: The boost inductor is selected according to formula (33). Here, two 60uH inductors are used.

Since the peak voltage stresses on the diodes D1, D2, D3, D4 are equal to half of the output voltage Vo, the block voltage of the diodes are chosen to be Vo for twice the voltage stress concern.

V. SIMULATION AND EXPERIMENTAL RESULTS

The specifications for the simulation are shown in Table IV. A prototype of the proposed converter plotted in Fig. 1 is implemented. The prototype is operated with the parameters shown in Table V.

TABLE IVSIMULATION SPECIFICATION OF THE PROPOSED CONVERTER

TABLE VPARAMETERS OF THE PROTOTYPE

The saber simulation waveforms of the proposed converter are shown in Fig. 6.

Fig. 6.Simulation waveforms.

The simulation waveforms verify the principle of the proposed converter and the feasibility of the operation is validated.

Fig. 7 shows the ZCS realization of the rectifier diodes. In Fig. 7(a), iD1 and iD2 decrease to zero before the diodes D1, D2 are reverse biased, and D1, D2 achieve ZCS turn-off. Analogously, D3, D4 achieve ZCS turn-off as shown in Fig. 7(b). From the waveforms, it is noted that the reverse-recovery problem has been removed.

Fig. 7.Voltage/current waveforms of the rectifier diodes. (a) Waveforms of D1, D2. (b) Waveforms of D3, D4.

Fig. 8 shows the voltage and current waveforms across the primary/secondary windings of the transformer. The primary/secondary winding currents agree with the theoretical analysis and the primary voltage spike is suppressed partly due to the clamp capacitor. A high frequency resonance occurs as shown in Fig. 8(a) because of the parasitic capacitor of the transformer. This will kill the system efficiency.

Fig. 8.Voltage/current of transformer windings. (a) Primary winding. (b) Secondary winding.

Fig. 9 shows the input/output characteristic of the proposed converter. The ripple of the input current is reduced greatly as shown in Fig. 9(a). Due to the symmetrical duty cycle of the switches S2, S4, the two boost inductors work in an interleaved way to be charged or discharged, and the input current is almost ripple free. Fig. 9(b) shows the input/output voltage and the current waveforms together. The output voltage drops to 188V from the theoretical 200V under the open loop control due to the output impedance. The voltage drop includes the device (MOSFETs and rectifier diodes) drop voltage and the transformer voltage drop. It is noted that the output voltage is almost ripple free due to the alternate charging and discharging of the output capacitors.

Fig. 9.Input/output characteristic of the proposed converter. (a) Current waveforms of iL1,iL2, Iin. (b)Input/output voltage and current.

Fig. 10 shows the voltage of the switched-capacitors. Vc1a and Vc1b are the dc voltages with a sinusoidal ripple determined by the resonant parameters and load as calculated in (34)(35), Vc2a and Vc2b have relatively large capacitances. As a result, the voltage is basically constant. In theoretical calculation, Vc2a = Vc2b=100V.

Fig. 10.Switched-capacitors voltage.

In Fig.11, the voltage spike of the main switches is reduced by the active-clamp circuit. The clamp-capacitor voltage calculated from (22) is 25V for a duty cycle that is close to 0.5. Hence, S3 (the drain-source voltage of the auxiliary switch) along with Vds3 and Vds4 (the drain-source voltage of the main switch S4) are clamped to be about 50V, which agrees with the theoretical waveforms. It should be mentioned that ZVS turn-on/off is realized for the switch S3.

Fig.11.Drain-source voltage waveforms of switches S3&S4 and current waveforms of switches S3&S4.

With the selected parameters, the estimated power loss distribution is calculated and summarized in Fig.12. The loss includes the main switches conduction loss PInput_MC, the main switches switching loss PInput_MS, the clamp switches conduction loss PInput_C, the input-side boost inductors conduction loss PInput_L, the output-side diodes conduction loss POutput_D, the magnetic core loss of the transformer PMag_Core, the primary copper loss of the transformer PMagPri_Co, and the secondary copper loss of the transformer PMagSec_Co. It can be found that the main switches loss and the primary copper loss are dominant for the loss distribution. The estimated efficiency at a 400w load with a 25V input and a 200V output is about 94.86%.

Fig. 12.Loss breakdown distribution at 400-W load.

The main switches conduction loss and the primary copper loss of the transformer are dominant due to a high primary current. In addition, the output diodes conduction loss covers a relative breakdown because of the relative high forward voltage of the diodes. Since the diodes are turned off at ZCS, it is better to utilize diodes with a lower forward voltage to promote system efficiency.

The measured efficiency of the proposed converter under all load conditions is presented in Fig.13. The maximum efficiency is over 94.79% at a 300-W load. Due to ZCS realization for all of the rectifier diodes and ZVS turn-off/turn-on realization for the auxiliary switches S1, S3. The efficiency of the proposed converter is high but relatively low at a light load since the basic loss weight increases in the whole power range.

Fig.13.Measured efficiency.

VI. CONCLUSION

This paper presents a high step-up DC-DC converter for photovoltaic power systems. The characteristic of the proposed converter can be summarized as follows: