I. INTRODUCTION

Full-bridge converters with a high power density and high efficiency have been proposed and used in many industry products such as server power units [1], telecommunication power units [2], and electric vehicle (EV) and plug-in hybrid electric vehicle (PHEV) battery chargers [3], [4]. Single-phase power factor correction (PFC) is normally adopted in the front stage to eliminate the current harmonics, increase the input power factor and keep the dc bus voltage at a constant voltage against line voltage and load current variations. For medium/high power ratings, power converters with a three-phase ac utility are adopted to reduce the current rating from the ac source. The power factors of these converters are normally required to improve the power quality of utility systems. Three-phase PFC with a unidirectional or bidirectional power flow and bridge/bridgeless circuit topologies can be adopted in the front stage. However, the dc bus voltage of the three-phase PFC will be higher than 750V or 800V. Thus, the power switches in the dc-dc converters of the rear stage must have 900V or 1200V voltage stress. Three-level dc-dc converters [5]-[7] with low voltage stress of the active switches are widely used in industry applications due to their high switching frequency and small size demands. Phase-shift pulse-width modulation (PWM) is normally adopted to generate the gate voltages of three-level converters. The main drawback of phase-shift PWM is that the lagging-leg switches have a narrow range of ZVS operation due to the limited energy stored in the primary leakage inductance. To overcome this problem, a large leakage inductance [8] or an external resonant inductance [3] can be placed on the primary side to extend the ZVS range of the lagging-leg switches. However, this approach also increases the duty cycle loss and decreases the effective duty cycle on the secondary side. In [9], [10], auxiliary circuits are added on the primary side to increase the ZVS load range. The switching power losses of the switches are improved. However, the power losses of the additional auxiliary circuits will decrease the total circuit efficiency. Recently, an LLC converter and a full-bridge converter sharing lagging-leg switches have been studied in [11], [12]. Thus, the ZVS range of the switches can be extended from zero to full load conditions. The other main problem of the phase-shift PWM scheme for full-bridge converters and three-level converters is its high circulating current during the freewheeling interval. To overcome this drawback, active or passive clamp circuits [4] and [13] can be added on the secondary side to limit voltage overshoots and oscillations across the output diodes when they are turned off, and to improve the circulating current losses on the primary side. However, an additional gate driver is needed to control the secondary active switch which will increase the circuit complexity and decrease the circuit reliability.

A hybrid three-level ZVS converter is studied in this paper to have the advantages of wide range of ZVS operation and low circulating current losses. The proposed hybrid converter combines a conventional three-level PWM converter and a half-bridge LLC converter with fixed switching frequency sharing of the lagging-leg switches to reduce the switch counts. Since the switching frequency of the LLC converter is greater than the series resonant frequency, the active switches at the lagging-leg can be turned on under ZVS from zero to full load conditions. The output voltages of the half-bridge LLC converter and the three-level PWM converter are connected in series. Thus, energy can be transferred from the input to the output load within the whole switching cycle. A passive snubber is adopted on the secondary side to provide a positive rectified voltage during the freewheeling interval to decrease the primary side current. Thus, the high circulating current in the conventional three-level PWM converter is rapidly reduced and the converter efficiency is improved. In the meantime, the rectified voltage on the secondary side during the freewheeling interval is positive instead of zero in the conventional three-level converter. The output inductance in the proposed hybrid converter can also be reduced. Finally, experiments with a 1.44kW prototype circuit are provided to demonstrate the performance of the proposed converter.

II. PROPOSED CONVERTER

Fig. 1 shows a general three-phase ac-dc converter for industry power units. The front-stage is a three-phase power factor corrector to achieve a low total harmonic distortion of the three-phase line currents, a high power factor and a stable high dc bus voltage. The second stage is a high frequency link dc-dc converter based on a full-bridge converter with IGBT power switches or a three-level PWM converter with power MOSFETs to provide a stable low dc bus voltage and high load current. In order to reduce the converter size and weight, a three-level PWM converter with power MOSFETs and a high switching frequency is generally used to achieve this demand. Fig. 2 shows a circuit diagram of the proposed high frequency dc-dc converter to overcome the disadvantages of conventional three-level PWM converters. There are two sub-converters in the proposed dc-dc converter. One is a three-level PWM converter (Cd1, Cd2, D1, D2, Cf, S1-S4, T1, Lr1, Dr1, Dr2, Cc, Da, Db, Lo and Co1) and the other is an LLC circuit (Cf, S2, S3, Lr2, Cr, T2, Dr3, Dr4 and Co2). S1 and S4 are in the leading-leg, and S2 and S3 are in the lagging-leg. The LLC circuit is operated at a fixed switching frequency so that the output voltage Vo2 is un-regulated. However, the total output voltage Vo is regulated by the three-level PWM circuit using the phase-shift PWM scheme. The energy stored in the output inductor Lo is reflected to the primary side to help the leading-leg switches turn-on at ZVS from light load to full load conditions. The LLC circuit, sharing the lagging-leg switches S2 and S3 of the three-level PWM circuit, is operated at a fixed switching frequency. The adopted switching frequency fsw is close to the series resonant frequency fr in the LLC circuit. The lagging-leg switches S2 and S3 can be turned on at ZVS from nearly zero to full load conditions. Thus, power switches S1-S4 in the proposed circuit have a wide range of ZVS operation when compared to the ZVS range in the conventional three-level converter. In order to reduce the circulating current of the three-level converter, a passive snubber circuit including Cc, Da and Db is used on the secondary side to provide a dc voltage during the freewheeling interval. During the freewheeling interval, the rectified voltage vr=vCc. The reflected voltage n1vr is applied to Lr1 on the primary side to reduce the circulating current to zero, and the output inductor voltage vLo=vCc-vo1 instead of -vo1. Thus, the high circulating current losses in the conventional three-level converter are improved in the proposed converter. Since the output voltages of the three-level circuit and the LLC circuit are connected in series, the input energy of the LLC circuit can be delivered to the output load in the whole switching cycle.

Fig. 1.Three-phase ac-dc converter with two-stage conversion.

Fig. 2.Circuit diagram of the proposed hybrid ZVS converter.

III. OPERATION PRINCIPLES

In the proposed converter, the turn-on time of each power switch is equal to half of a switching period. The PWM signal of S2 (S3) is phase-shifted with respect to the PWM signal of S1 (S4). S1 (S2) and S4 (S3) operate complementarily with a short dead time to avoid short circuits. The operation principles of the proposed converter are based on the following assumptions. 1) MOSFETs S1-S4 and rectifier diodes Dr1-Dr4, D1-D2 and Da-Db are ideal, 2) capacitor voltages vCd1, vCd2, vCf, Vo1 and Vo2 are constant, the turns ratios of T1 and T2 are n1=np1/ns1 and n2=np2/ns2, respectively, and 3) C1=C2=C3=C4=Coss and VCd1=VCd2=VCf=Vin/2. Fig. 3 illustrates the key PWM waveforms of the proposed converter in a switching cycle. According to the switching states of S1-S4, Dr1-Dr4, D1-D2 and Da-Db, the converter has seven operation modes in each half of a switching period. Fig. 4 gives the equivalent circuits for the seven operation modes.

Fig. 3.Key waveforms of the proposed converter during one half of switching cycle.

Fig. 4.Operation modes of the proposed converter in a half switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7.

Mode 1 [t0 - t1]: Prior to t0, the power semiconductors S1, S2, Dr1 and Dr3 are conducting. Both of the inductor currents iLr1 and iLr2 are positive. S1 is turned off at t0. C1 and C4 are charged and discharged, respectively, by iLr1. The energy stored in the output inductor Lo and the primary inductor Lr1 is used to discharge C4 to zero voltage. The ZVS condition of S4 is illustrated in (1).

This mode ends at t1 when vC1=Vin/2 and vC4=0. The time interval of mode 1 is given in (2).

The dead time between S1 and S4 must be greater than Δt01 to achieve the ZVS operation of S4.

Mode 2 [t1 - t2]: Mode 2 starts at t1 when vC1=Vin/2, vC4=0, and D1 and Da are on. Since iLr1 is positive, the output diode of S4 is conducting. At this moment, S4 can be turned on under ZVS. In this mode, the primary side voltages vab=0 and vac=vCf=Vin/2 in the steady state. Since Da is on, the rectified voltage vr=vCc and vLo=vCc-Vo1<0. The inductor current iLo decreases with a slope of (vCc-Vo1)/Lo. The reflected secondary windings voltage -n1vCc is applied to Lr1 so that the primary side current iLr1 rapidly decreases to zero with a slope of -n1vCc/Lr1. The time interval in mode 2 is obtained in (3).

In the conventional three-level converter, the primary current iLr1 in this mode is kept at the same value of iLr1(t1) because vLr1=0. Thus, the conventional three-level converter has large circulating current losses during the freewheeling interval. The energy stored in the clamped capacitor Cc is transferred to the output load through Lo and Da. The secondary winding current ia decreases in this mode. The LLC converter is still in the resonant mode to transfer energy from the input to the output load.

Mode 3 [t2 - t3]: Mode 3 starts at t2 when the secondary winding current ia decreases to zero, and the capacitor current iCc=-iLo. The primary side current iLr1 is approximately zero and the primary and secondary sides of T1 are disconnected. There is no circulating current loss in this mode. The output inductor voltage vLo=vCc-Vo1<0 and iLo decreases. The LLC circuit continuously transfers energy from Cf to the output load.

Mode 4 [t3 - t4]: Mode 4 starts at t3 when S2 is turned off. iLr2 charges C2 to Vin/2 and discharges C3 to zero. The LLC converter is operated at fsw (switching frequency) ≈ fr (series resonant frequency). Thus, the inductor current iLr2 is lagging with respect to the input fundamental voltage vac,f.

Mode 5 [t4 - t5]: Mode 5 starts at t4 when the capacitor C3 is discharged to zero. Since iLr1(t4)+iLr2(t4)>0, the anti-parallel diode of S3 is conducting. S3 can be turned on under ZVS due to the help of the LLC converter. In this mode, Da, Dr2 and Dr4 are on, vab=-Vin/2, vac=0, and vr=vCc. The output inductor voltage vLo=vCc-Vo1<0 and iLo decreases. The primary inductor voltage vLr1=n1vCc-Vin/2<0 so that iLr1 decreases with a slope of (n1vCc-Vin/2)/Lr1 until ia=iLo. In the LLC converter, Cr and Lr2 are resonant with the input voltage vac=0, and iLr2 decreases in this mode. During this time interval, ia increases from zero to iLo, and iCc increases from -iLo to zero. The time interval in this mode is given as:

In this mode, the three-level converter and the LLC converter transfer energy from the input to the output load. The ac terminal voltage vab=-Vin/2 and diode Da conducts to obtain the rectified voltages vr=vCc. The duty loss in mode 5 is given as:

Mode 6 [t5 - t6]: Mode 6 starts at t5 when ia=iLo and iCc=0. Diode Da is off. The reflected primary inductance Lr1/(n1)2 and Cc are resonant with the resonant frequency . Thus, the diode Db is conducting in this mode. The output inductor current iLo increases with a slope of vCc/Lo. The half of a resonant period, 1/(2fR), is designed to be less than the minimum effective duty cycle time (δeff,minTsw/2). Then, the capacitor current iCc will be decreased to zero before S4 is turned off. The rectified voltage vr=vCc+Vo1, and the primary inductor current iLr1=-(iLo+iCc)/n1. In this mode, energy is transferred from the input voltage to the output load through both the three-level converter and the LLC circuit.

Mode 7 [t6 - t7]: Mode 7 starts at t6 when iCc=0, and diode Db is off. The rectified voltage vr≈Vin/(2n1)>vCc, and Da is reverse biased. The output inductor voltage vLo=Vin/(2n1)-Vo1>0, and iLo increases in this mode. This mode ends at t7 when S4 is turned off. Then, the circuit operations of the proposed converter in the first half of a switching period are completed.

IV. CONVERTER PERFORMANCE ANALYSIS

There are two circuits, a three-level PWM circuit and an LLC circuit, in the proposed converter. The three-level converter transfers energy from the input voltage Vin to the output Vo1 in modes 5-7 during the first half of the switching cycle. The LLC converter transfers energy from the capacitor Cf to the output Vo2 within a full switching period. Since the LLC converter is operated as an unregulated dc-dc converter with a switching frequency fsw that is close to the series resonant frequency fr, the lagging-leg switches S2 and S3 are easily turned on at ZVS from zero to full load, and the circulating current of the LLC converter is at its minimum due to fsw≈fr. Based on the fundamental frequency analysis of the LLC converter, the ac voltage gain of the LLC converter at the switching frequency is equal to unity. Thus, the designed dc voltage gain of the LLC circuit is equal to the ac voltage gain of the LLC circuit at the series resonant frequency, i.e. Mdc,LLC=4n2Vo2/Vin=1. The unregulated output voltage Vo2 of the LLC converter is obtained as:

The ZVS condition of the leading-leg switches S1 and S4 is achieved by the primary inductance Lr1 and output inductance Lo given in (1). The other ZVS condition of S1 and S4 is that the dead time between S1 and S4 must be greater than Δt01 given in (2). The charge and discharge times of S1-S4 are much less than the time intervals in the other modes, and only modes 2, 3, 5, 6 and 7 are considered in the following analysis. In mode 6, the average capacitor voltage VCc=Vin/(2n1)-Vo1. The flux balance condition on the output inductance Lo is given as:

where δ6 is the duty cycle in mode 6. Substitute VCc=Vin/(2n1)-Vo1 into (7). Then, the output voltage Vo1 of the three-level converter is obtained as:

where the effective duty cycle δeff=δ-δ5, and δ is the duty ratio of the proposed converter when (S1 and S2) or (S3 and S4) are in the on-state. The output voltages of the three-level converter and the LLC converter are connected in series so that the output voltage Vo of the proposed converter is expressed as:

The dc voltage conversion ratio of the proposed converter is obtained as:

The ripple current of the output inductor Lo is approximated as:

From (11), the output inductance Lo is obtained in (12).

The ripple currents, the maximum currents and the minimum currents of the magnetizing inductances Lm1 and Lm2 are obtained as:

The average diode currents of D1-D4 Db are shown in (16) and (17).

The voltage stresses of D1-D4, Da and Db are given as:

V. EXPERIMENTAL RESULTS

First, the design procedure of the proposed converter is shown in this section to derive the main circuit components in a laboratory prototype. The electric specifications of the prototype circuit are Vin=750V-800V, Vo=48V and Io,rated=30A. The switching frequency fsw=100kHz. The output voltage of the LLC converter is assumed as 20V. The selected series resonant frequency of the LLC converter is equal to the switching frequency fsw. The DC gain of the LLC converter at fr is equal to unity. Based on (6), the turns ratio of T2 is obtained in (21).

The primary inductance, primary winding turns and secondary winding turns of T2 are 480μH, 30 turns and 3 turns, respectively. In the LLC converter, the series resonant inductance Lr2=80μH and the series resonant capacitance Cr =32nF. The series resonant frequency of the LLC converter is close to 100kHz. The maximum effective duty cycle δeff is assumed to be 0.4. From (9), the turns ratio of T1 is derived in (22).

The magnetizing inductance, primary winding turns and secondary winding turns of T1 are 1.3mH, 64 turns and 6 turns, respectively. The assumed duty cycle loss in mode 5 is 0.01. The necessary primary inductance Lr1 can be obtained from (5) and is given in (23).

The selected primary inductance Lr1 is 10μH in the prototype circuit. From (12), the output inductance Lo is obtained in (24) with ΔiLo/Io,rated=0.2.

In the prototype circuit, the adopted output inductance Lo is 5μH. Power MOSFETs (IRFP460) with VDS=500V and ID,rms=20A are used for the switches S1-S4. Fast recovery diodes (VF30200C) with VRRM=200V and IF=30A are used as the rectifier diodes D1-D6, Da and Db. The selected clamped diodes D1 and D2 are MUR860. The selected input split capacitances are Cd1=Cd2=360μF/450V, the flying capacitance Cf=1μF and the output capacitances are Co1=Co2=2200μF.

Experimental results based on a laboratory prototype with the above circuit parameters are presented to verify the circuit performance. Fig. 5 gives the measured PWM signals of S1-S4 and the ac side voltages vab and vac at 25% and 100% loads. It can be seen that there are three voltage levels on vab and two voltage levels on vac. The measured voltage and current of S1(leading-leg switch) at 15% and 100% loads are illustrated in Fig. 6. Fig. 7 gives the measured voltage and current of S2 (lagging-leg switch) at 15% and 100% loads. From Figs. 6 and 7, S1 and S2 are all turned on at ZVS at a 15% load. (S1, S4) and (S2, S3) are in the leading-leg and lagging-leg, respectively. Thus, S1-S4 are all turned on at ZVS from 15% to full load conditions. Fig. 8 shows the test results of the ac side voltages vab and vac, the resonant capacitor voltage vCr, and the primary currents iLr1 and iLr2 at 25% and 100% loads. There is no circulating current on iLr1 in the freewheeling interval (vab=0), and the primary current iLr2 is a quasi-sinusoidal current. From the measured primary inductor current iLr1 in Fig. 8(b), it is clear than there are seven operation modes in the first half switching cycle and these measured waveforms verify the operation mode discussions in section III. Fig. 9 illustrates the experimental results of the diode currents iD1-iD4, clamped capacitor current iCc, output inductor current iLo, three-level converter output current iTL,o=iLo+iDb, LLC converter output current iLLC,o and load current Io at full load. The measured circuit efficiencies of the proposed converter are 94.5%, 95.3% and 93.2% at a 25% load, a 50% load and a 100% load, respectively. The measured maximum efficiency is 95.9% at an 80% load.

Fig. 5.Measured PWM signals of S1-S4 and ac side voltages vab and vac at (a) 25% load. (b) 100% load.

Fig. 6.Measured voltage and current of S1 (leading-leg switch) at (a) 15% load (b) 100% load.

Fig. 7.Measured voltage and current of S2 (lagging-leg switch) at (a) 15% load (b) 100% load.

Fig. 8.Measured waveforms of ac side voltages vab and vac, resonant capacitor voltage vCr, and the primary currents iLr1 and iLr2 at (a) 25% load (b) 100% load.

Fig. 9.Measured waveforms of diode currents iD1-iD4, clamped capacitor current iCc, output inductor current iLo, three-level converter output current iTL,o, LLC converter output current iLLC,o and load current Io at full load.

VI. CONCLUSION

A hybrid ZVS converter is presented in this paper to reduce the circulating current loss in the freewheeling interval and to extend the ZVS range of the lagging-leg switches. The proposed hybrid converter includes a conventional three-level converter and a LLC converter with shared lagging-leg switches. The switching frequency of the LLC converter is close to the series resonant frequency to reduce the circulating current at the primary side and to help the lagging-leg switches turn on at ZVS from light load to full load conditions. A passive snubber is used on the secondary side of the three-level converter to reduce the circulating current during the freewheeling interval due to the fact that a reflected rectifier voltage is applied to the leakage inductance. The outputs of the two converters are connected in series to transfer energy from the input to the output load within the whole switching cycle. When compared to the conventional three-level PWM converter, the proposed hybrid converter has less circulating current losses and a wider range of ZVS operation. Finally, the effectiveness and performance of the proposed converter are verified by experimental results with a 1.44kW prototype circuit.