1. Introduction

In the last few years, the most digital implementations of control algorithms of electric machines are based on software solutions such as microcontrollers and digital signal processor. However, these solutions present some disadvantages; for example, the used sampling period is limited by the time of computation. To overcome the traditional software solution limitations, new hardware solutions such as the FPGAs can be used, which present the appropriate digital solutions for the implementation of control algorithms. The inherent parallelism of these new digital solutions as well as their large computing capacity, making computation time delays, are negligible despite the complexity of the algorithms to implement.

The conventional direct torque control of the induction motor is characterized by outstanding dynamic performances as well as good robustness to against changes of motor parameters. However, the Conventional Direct Torque Control (CDTC) also has some drawbacks, like high electromagnetic torque and stator flux ripples and high stator current distortion [1-3]. To improve the CDTC performances, many methods are used, such as the fuzzy logic control, the Space Vector Modulation (SVM) [4-6], and the increase in the switches inverter number [7]. Nevertheless, the use of SVM needs several motor parameters and increases the complexity of the Direct Torque Control (DTC) algorithm. Moreover, the rise in the switches inverter number increases costs. In this work, our orientation is focused to the fuzzy logic control, because it is an effective technique used where mathematical model is complicated or the mathematical model does not exist, as well it is allows controlling the systems without knowing the mathematical model. The objective of this work is to implement the Direct Torque Fuzzy Control (DTFC) of the induction motor on the FPGA in order to take advantage of these performances in the field of digital control of electrical machines in real time. The Fuzzy Logic Control (FLC) is used to replace the switching table, the sector block and the two hysteresis comparators [8].

During the last few years several researchers use the hardware implementation on the FPGA for controlling electrical system [9-15]. Most of them use the VHDL (VHSIC hardware description language). In this study, the Xilinx System Generator (XSG) is used to automatically generate the VHDL code. The advantages of this method are the rapid time to market, real time, and portability.

 

2. Contributions of Xilinx System Generator

The XSG is a modeling tool developed by the Xilinx to design implemented systems on the FPGA. It has a library of varied blocks, which can be automatically compiled into an FPGA [16]. In this work, the (XSG) is used to implement the DTFC architecture of the induction motor based on Fuzzy Logic Control (FLC) algorithm on an FPGA. In the first step, we begin by implementing the proposed architectures using the XSG blocks available on the Simulink library. Once the Design of the system is completed and gives the desired simulation results, the VHDL code can be generated by the XSG tool [17]. The design flow of the XSG is given in Fig. 1. After generating the VHDL code and the synthesis, we can generate the bitstream file. Then we can move this configuration file to program the FPGA [18].

Fig. 1.Xilinx system generator design flow

 

3. Basic CDTC Principle of Induction Motor

3.1 Induction machine model

The model of the induction motor expressed in the stationary “αβ” axes reference frame can be described by [19]:

where, iS, φS, VS, R, and L denote the stator currents, stator flux, stator voltage, resistance, and inductance, respectively, and where ω denotes the rotor speed and is the redefined leakage inductance.

The electromagnetic torque of the induction motor can be expressed in terms of stator currents and stator flux, which is given by the following expression:

The mechanical speed equation is given by the following equation:

where p is the number of pole pairs, J and TL denote the moment of inertia of the motor and the load torque, Ω is the rotor mechanical speed (pΩ=ω), and f is a viscous friction coefficient.

3.2 CDTC Principle

The basic principle of the CDTC is based on the application of a voltage particular sequence via a voltage inverter, whose waves are generated through hysteresis comparators in which the flux and torque are trapped to follow their references [20]. The components of the stator voltage vector in the stationary reference frame are calculated as follows:

where Vdc is the DC bus voltage.

The components of the stator current vector are given by the following expression:

The module of the stator flux is given by Eq. 6:

The angle between the stator flux ϕs (ϕsα, ϕsβ) and the reference axis is given by Eq. (7):

The estimated values of the torque and stator flux are compared to the reference values Te* and φS* , respectively. It can be seen from Fig. 3 that the error between the estimated torque Te and the reference torque Te* is the input of a three level hysteresis comparator, where the error between the estimated stator flux magnitude φS and the reference stator flux magnitude φS* is the input of a two level hysteresis comparator.

Fig. 3.Basic direct torque control scheme

Finally, the outputs of the comparators with a stator flux sector, where the stator flux space vector is located, select an appropriate inverter voltage vector from the switching table (Table 1). The selected voltage vector will be applied to the induction motor at the end of the sample time [21].

Table 1.Switching table for conventional DTC

The vectors V1,...,V6 represent the six active vectors that can be generated by a voltage source inverter where V0 and V7 are the two zero voltage vectors. Fig. 2 gives the partition of the complex plan in six angular sectors Si=1...6.

Fig. 2.Partition of the complex plan in six angular sectors

When the stator flux is in zone i, the vector Vi+1 or Vi−1 is selected to increase the level of the flux, and Vi+2 or Vi−2 is selected to decrease it. At the same time, the vector Vi+1 or Vi−2 is selected to increase the level of the electromagnetic torque, and Vi−1 or Vi−2 is selected to decrease it.

If V0 or V7 is selected, the rotation of the stator flux is stopped and the torque decreases, whereas the amplitude of the stator flux remains unchanged. This shows that the choice of the vector tension depends on the sign of the error of the stator flux and electromagnetic torque independently from their amplitude [21]. This explains why the output of the hysteresis comparator of the stator flux and torque must be a Boolean variable. We can add a band of hysteresis around zero to avoid useless commutations when the error of the stator flux is very small [21].

With this type of hysteresis comparator, we can easily control and maintain the end of the vector flux within a circular ring.

The basic structure of the CDTC induction motor is shown in Fig. 3.

 

4. DTC Based On Fuzzy Logic Control

The fuzzy approach is proposed to reduce the torque, flux and current ripples. The fuzzy logic controller has been introduced to replace the two hysteresis controllers and the switching table. Fig. 4 illustrates the structure of the fuzzy DTC of induction motor. The inputs of the fuzzy controller bloc are the torque error, flux error and stator flux angle. The voltage vector is the output.

Fig. 4.Fuzzy direct torque control (DTCF) scheme

4.1 Fuzzy logic controller principle

In the fuzzy logic controller system, we can distinguish three main parts: fuzzification, fuzzy reasoning and defuzzification [22]. The fuzzification is based on the membership functions.

4.2 Fuzzy variables

The membership function of the stator flux error is given by three linguistic terms: Negative (N), Zero (Z) and Positive (P), as shown in Fig. 5(a). The error of the stator flux is given by the following equation:

Fig. 5.(a) Fuzzy membership functions of the flux error ( eϕ); (b) Fuzzy membership functions of the torque error eT

The membership function of the electromagnetic torque error is given by five linguistic terms: Negative Large (NL), Negative Small (NS), ZEro (ZE), Positive Small (PS) and Positive Large (PL) and shown in Fig. 5(b). The error of the electromagnetic torque is given by the following equation:

The membership function of the angle θs is given by twelve fuzzy sets:θ1 ,θ2, θ3, θ4, θ5, θ6, θ7, θ8, θ9, θ10, θ11, and θ12 as shown in Fig. 6.

Fig. 6.Stator flux position membership function

The membership functions of the output space voltage vectors are shown in Fig. 7.

Fig. 7.Fuzzy membership functions of output

A system with three inputs, one having three fuzzy sets, another having five fuzzy sets, and the other having twelve fuzzy sets, has a total of 3*5*12=180 different control rules shown in Table 2.

Table 2.Fuzzy control rule table

Each control rule can be described using the three input variables: the stator flux error ef , the electromagnetic torque error eT and the angle θs and the output variable V as:

where Xi, Yi and Zi are the fuzzy sets ef , eT and θ,

4.3 Fuzzy inferences

In this work we use the inference method of Mamdani’s which is based on the min-max decision.

There are several methods of defuzzification, such as the method of the center of gravity and the maximum method. In our case, we have used the latter method. Fig. 8 shows the concrete reasoning of the fuzzy inference system.

Fig. 8.Steps of the fuzzy logic system for the DTFC technique

4.4 Design of membership functions using the xilinx system generator

The fuzzy logic controller bloc propagates the inputs (sator flux error ef , electromagnetic torque error eT , and angle θs ) to the output voltage vectors Vi. The structure of the fuzzy logic controller bloc is shown in Fig. 9.

Fig. 9.Fuzzy logic controller bloc from the Xilinx System Generator

The stator flux error is given by three fuzzy sets; evenly, we have three mathematical functions, named: P, Z and N. The membership function of N is given by Eq. 11 and illustrated using the XSG, as in Fig. 10.

Fig. 10.Design of the membership function N of the stator flux error from the XSG

The electromagnetic torque error is given by five fuzzy sets; evenly, we have five mathematical functions, named: NL, NS, ZE, PS and PL. The membership function of ZE is given by Eq. 12 and illustrated using the XSG, as in Fig. 11.

Fig. 11.Design of the membership function ZE of the electromagnetic torque error using the XSG

The angle θs is given by twelve fuzzy sets:

θ1, θ2, θ3, θ4, θ5, θ6, θ7, θ8, θ9, θ10, θ11, and θ12 .

The membership function of θ4 is given by Eq. 13 and illustrated using the XSG, as in Fig. 12.

Fig. 12.Design of the membership function θ4 of θs error using the XSG

4.5 Rules design

In this work we use the inference method of Mamdani’s which is based on the min-max decision. The output of each fuzzy rule is given by the minimum function between the three membership functions of the stator flux error Δφ , the electromagnetic torque error ΔTe , and the angle θS . The design of rule number 26 using the XSG is given by Fig. 13.

Fig. 13.

R26: If ( ef is N) & ( eT is PL) & (θs is θ5 ), then (V is V1)

4.6 Rules interconnection

To move from one rule to another, the OR operator is used. This operator is presented by the Maximum function and connects all rules. The output presents the maximum value between the inputs. The design of the Max block for the rules with the output voltage vector Vi is given by Fig. 14.

Fig. 14.Design of the maximum block connecting the V1 output rules

4.7 Control vector block

For each sampling period, three Boolean variables (Sa, Sb, Sc) are determined for each selected voltage vector Vi. The control vector block is illustrated using the XSG, as in Fig. 15.

Fig. 15.Calculation of sequences (Sa, Sb, Sc) using the voltage vector

 

5. Simulation Result and Discussion

The simulation of the CDTC and the DTFC of the induction motor is achieved using the XSG. The flux reference is 0.91 (wb), and the system period is 50µs. The reference of the electromagnetic torque is the output of the proportional integral controller of the rotor speed. The load torque is applied at the times t=0.3sec and t=0.6sec. For the two CDTC and DTFC techniques we obtain the evolution of the rotor speed, the stator flux, the electromagnetic torque, the stator current module, and the sinusoidal distribution of the stator current, which are given by Fig. 16-19, and Fig. 20, respectively.

Fig. 16.Evolution of the rotor speed: (a) CDTC; (b) DTFC

Fig. 17.Evolution of the stator flux: (a) CDTC; (b) DTFC

Fig. 18.Evolution of the electromagnetic torque: (a) CDTC; (b) DTFC

Fig. 19.Evolution of the stator current module: (a) CDTC; (b) DTFC

Fig. 20.Evolution of the stator current: (a) CDTC; (b) DTFC

In Fig. 16, the rotor speed has quickly reached its reference value, 150 rd/s, which shows the high dynamics of the DTC.

In Fig. 17, the stator flux has quickly attained its reference value, 0.91 wb, which shows the high dynamics of the DTC. The stator flux in the case of the CDTC is characterized by high ripples, which has decreased by using the fuzzy logic.

The evolution of the electromagnetic torque is given by Fig. 18. We can notice that the electromagnetic torque ripples is reduced in the case of the DTFC.

In Fig. 19, it can be seen that the stator current ripples is reduced by using the FLC. In Fig. 20, we can notice that the stator current distortion is reduced in the case of the DTFC.

From the simulation results we can have the Table 3 to compare the results observed in the case of the CDTC and the DTFC.

Table 3.Advantages of DTFC in terms of ripples

 

6. DTFC Implementation on FPGA

From the DTFC design, using the XSG, we can automatically generate the VHSIC Hardware Description Language (VHDL) code to be implemented into the FPGA. The implementation results of the CDTC and the DTFC are given in Fig. 21 which shows the RTL (Register Transfer Level) schematic of the DTFC in the Xilinx ISE 12.4 and given in the Table 4 that presents the used resources.

Fig. 21.Synthesis result of the DTFC using the Xilinx ISE 12.4

Table 4.Used resources

The performance of the hardware implementation on FPGA in term of processing speed is shown in Table 5.

Table 5.FPGA performance in terms of computing time

To control the industrial systems like the induction motor, two main families of digital devices such as the microcontroller, the Digital Signal Processor (DSP) and the FPGAs. The first family is based on the microcontroller and the DSP controllers. These components integrate a microprocessor and several peripherals used for the communication with the industrial environment. The general-purpose microcontrollers include a 16-bit or 32-bit Reduced Instruction Set Computer (RISC) core and different peripherals, such as the STM microcontrollers (STM32F3, STM32F4, STM32F1…) [23, 24]. The main limitation factor of the general purpose microcontroller is the computing power. This limit allows fixing the sampling period. The DSP controllers integrate a high performing processor core based on a hardware accelerator computing block and few peripherals. In the field of the control of the induction motor, the digital signal processor dSPACE (dSPACE 1102(DSP TMS320), dSPACE 1103(DSP TMS 320 F240), and dSPACE 1104 (DSP TMS320 F240)) is so much used, but the main limitations of this solution is the low processing speed due to the sequential processing [25-27] compared to the FPGA. The programming language of these solutions is the ‘C’ code [28], but in most cases the Matlab/Simulink is used to program these circuits [25, 32]. General-purpose microcontrollers are characterized by their low price [29]. But are not recommended for the complex algorithms due to its low processing speed relative to the FPGA and dSPACE. In Table 4, it is clear that the used resources are negligible relative to the available resources. Therefore, in the industrialization phase we can choose an FPGA with a few resources and a low price. In [30] The FPGA is inexpensive relative to the dSPACE, and it can execute in real time, with a very low execution time, a full complex algorithm, this due to its processing parallelisms. Therefore, the cost of the system based on the FPGA is lower compared to that based on the dSPACE.

The performances of the hardware solution based on the FPGA compared to software solutions (general-purpose microcontroller (STM 32F4…), Digital Signal Processor dSPACE 1104), is shown in Fig. 22.

Fig. 22.Timing diagram for the implementation on: (a) General-purpose microcontroller (STM 32F4…); (b) Digital Signal Processor and Control Engineering (dSPACE 1104); (c) Xilinx Virtex-V FPGA with an xc5vfx70t-3ff1136 package

The computing power of the dSPACE 1104 is greater than that of the STM32 microcontroller due to their adapted architecture. The papers [31-34] present the digital control of the induction motor using the dSPACE 1104. In these papers, the sampling time is 100µs, due to the sequential processing of the dSPACE. In paper [25], the execution time is of 300µs using the dSPACE 1102. Using the FPGA, the execution time of the control algorithm of the induction motor is ( ≈ 1 to 2µs). Therefore, the obtained execution time using the FPGA is far lower compared to the programmed solution. In this paper, the execution time of the DTFC algorithm is of 0.89µs, using the Xilinx Virtex-V FPGA with an xc5vfx70t-3ff1136 package.

 

7. Conclusion

In this paper, an intelligent technique based on the Fuzzy Logic Control is used to improve of the performances of the Conventional Direct Torque Control of the induction motor. In the Direct Torque Fuzzy Control the switching table, the sector block, and the hysteresis comparators of the stator flux and electromagnetic torque are replaced by the intelligent technique. The main improvements shown are the reduction in the stator flux, the electromagnetic torque ripples and the stator current distortions. Comparatively, the execution time is very weak.

This Direct Torque Control with the Fuzzy Logic Control is designed to be implemented on the Field Programmable Gate Array (Xilinx Virtex-V FPGA) using the Xilinx System Generator, which presents an interesting approach. Its use is very practical since the HDL knowledge is unnecessary and so the implementation time is reduced. Thus, the obtained design can be translated automatically into a VHDL programming language and can be embedded into the Xilinx Virtex-V FPGA application board.