I. INTRODUCTION

The conventional control method for two-level inverters is very simple and easily implemented. However, there are some drawbacks, such as high total harmonic distortion (THD) of the output waveforms, high voltage stress of the switching devices, low system efficiency and so on [1]-[3]. This is especially true in middle and high voltage, or high power conversions. Akira Nabae proposed a new neutral-point clamped (NPC) PWM inverter in 1980, which is the basic three-level inverter [1]. Comparing with the conventional two-level inverter, the three-level inverter has many advantages, such as low voltage stress on switching devices, high equivalent switching frequency, reduced output harmonics, etc. [4]-[6]. Therefore, it is widely used in middle and high voltage, or high power applications [1], [4].

In order to generate phase voltage with three-levels and line voltage with five-levels, the NPC three-level inverter circuit needs two DC bus capacitors connected in series between the positive and negative poles of the DC bus. Ideally, the voltage on each capacitor is half the DC bus voltage. However, due to capacitance errors of the capacitors, different parameters of the switching devices, unbalanced three-phase operation, and other factors[12], a DC bus neutral-point voltage unbalancing problem appears, which influences the output waveforms quality[2], [6]. In addition, this problem makes the output waveforms containing a lot of low frequency harmonics. When the neutral-point voltage unbalancing problem becomes serious, it damages the switching devices and affects the system operation [6]. To solve this problem, many methods have been proposed [2]-[13].

The neutral-point voltage unbalancing problem contains two parts: the dc deviation and the low frequency oscillation of the neutral-point voltage. The dc deviation of the neutral-point voltage can be controlled by many solutions proposed in the literature. For example, zero-sequence voltage injection methods have been proposed in [2], [7], Ref. [3], [5] propose improved space vector modulation (SVM) methods to reduce the neutral-point voltage unbalancing. In addition, they correctly select other vectors, which do not impact on the neutral-point voltage, to replace the small vectors.

The low frequency oscillation of the neutral-point voltage can lead to a lot of low frequency harmonics in the output waveforms, and the voltage stress of the switches is increased [4], [10]-[11]. When the dc deviation of the neutral-point voltage appears, the low frequency oscillation problem can also exacerbate the neutral-point voltage unbalancing, especially in middle or high power applications. However, the low-frequency oscillation problem of the neutral-point voltage is commonly ignored.

Ref. [9], [11] analyze the low frequency oscillation of the neutral-point voltage. However, a solution for this problem is not presented. In [10], a new modulation strategy using small vectors to compensate for the effects of all of the vectors in each carrier cycle is proposed to reduce the neutral-point voltage ripple. Ref. [4] proposes a double modulation waves strategy based on SPWM to enable the average neutral-point current to be zero. So the low frequency oscillation of the neutral-point voltage is eliminated. However, it has a much higher switching frequency when compared with the conventional SPWM control method.

Based on the basic principle of discontinuous pulse width modulation (DPWM), this paper proposes a new DPWM control method to suppress the low frequency oscillation of the neutral-point voltage. By distinguishing the odd and even carrier cycles, and the prior and latter half carrier cycles, the proposed method controls the switches of a certain phase so that there is no switching in each carrier cycle. In addition, in each carrier cycle, the operating time of the positive and negative small vectors in pairs is equal. Therefore, the average value of the neutral-point current is zero in a carrier cycle, and a neural-point voltage without low frequency oscillation can be achieved. When compared with the conventional SPWM control, without adding complex hardware circuits or increasing the switching frequency, the new DPWM control method proposed in this paper can suppress the low frequency oscillation of the neutral-point voltage effectively under different load conditions. This decreases the output waveforms harmonics and significantly increases the system efficiency. The proposed DPWM control method is easy to achieve with digital implementation. Experiments have been realized by a NPC three-level inverter prototype based on STM32F407-CPLD, and the experimental results verify the feasibility and effectiveness of the proposed method.

II. THE BASIC PRINCIPLE OF DPWM CONTROL

Fig. 1 shows the main circuit topology of a NPC three-level inverter. The nodal point connected to the DC bus capacitors C1 and C2 is neutral-point O for the NPC three-level inverter.

Fig. 1.Main circuit of NPC three-level inverter.

Take phase a as an example, its output leg consists of four switches (Sa1, Sa2, Sa3, Sa4), four anti-parallel free-wheeling diodes (Da1, Da2, Da3, Da4), and two clamping diodes (D1, D2).

“P”, “0”, and “N” represent three working states corresponding to the three output levels of the NPC three-level inverter. The neutral-point “O” is defined as the reference point, and the corresponding output levels and switching states are shown in Table I. Where Sxn (x=a, b, c, and n=1, 2, 3, 4) represents the four switches of each phase leg for the NPC three-level inverter in Fig. 1. Vdc is the input DC bus voltage. “√” and “×” represents the switching on and switching off states, respectively.

TABLE IOUTPUT LEVEL OF THREE LEGS AND SWITCHING STATES

The DPWM control method can keep switches no switching at specific areas in a line cycle, and its most significant advantage is reducing switching losses. Thus, the DPWM control method can improve the conversion efficiency of the inverter.

Three conventional control methods based on DPWM are the 120°DPWM, 60°DPWM, and 30°DPWM [14][15]. The 60°DPWM control method is shown in Fig. 2, where va, vb, vc represents the three-phase modulation waves for a NPC three-level inverter with the conventional SPWM control. It can be seen that the line cycle has been divided into six equal regions.

Fig. 2.The operating principle of 60°DPWM.

The regions are defined as follows:

I(0–π/3), II(π/3–2π/3), III(2π/3–π), IV(π–4π/3), V(4π/3–5π/3), and VI(5π/3–2π).

In each region, the switches of one certain phase keep no switching. So the corresponding output level is in the “P” or “N” state, the details are as follows:

(1) In regions I(0–π/3), III(2π/3–π), and V(4π/3–5π/3), for the phase modulation wave with the lowest voltage value, the corresponding switches Sx3, Sx4 of this phase are kept in the on-state, and the switches Sx1, Sx2 of this phase are kept in the off-state. Therefore, the output phase leg is in the “N” state,

(2) In regions II(π/3–2π/3), IV(π–4π/3), and VI(5π/3–2π), for the phase modulation wave with the highest voltage value, the corresponding switches Sx1, Sx2 of this phase are kept in the on-state, and the switches Sx3, Sx4 of this phase are kept in the off-state. Therefore, the output phase leg is in the “P” state.

When compared with the conventional SPWM control method, the 60°DPWM control method reduces the equivalent switching frequency by about 33% under resistive load conditions. As a result, it can reduce the switching losses and improve the conversion efficiency of the inverter. However, reducing the equivalent switching frequency causes some problems, which cannot be ignored, such as increasing the output harmonics and decreasing the quality of the output waveforms.

The three conventional DPWM control methods reduce the switching losses by controlling the switches no switching in certain regions [15]. However, they are commonly ineffective for the neutral-point voltage unbalancing control, especially for the low-frequency oscillation problem.

III. THE INFLUENCE OF THE REFERENCE SPACE VOLTAGE VECTOR ON THE NEUTRAL-POINT CURRENT

As shown in Table I, each phase of a NPC three-level inverter has three working states (P, 0, N). Therefore, the NPC three-level inverter has a total of 27(33) kinds of working states. Each working state corresponds to one reference space voltage vector. Thus, there are 27 reference space voltage vectors including 6 big vectors, 6 medium vectors, 12 small vectors, and 3 zero vectors.

When the zero vectors operate, the neutral-point current is zero. As a result, the zero vector has no effect on the neutral-point current. When the big, medium and small vectors operate, the flowing direction of the neutral-point current can be obtained.

The impact on the neutral-point voltage of the load currents is shown in Fig. 3 when the big vector [PPN], medium vector [P0N], positive small vector [PP0], and negative small vector [00N] operates, respectively. Where ia, ib, ic represents the three-phase load currents, vo represents the neutral-point voltage, and io represents the neutral-point current.

Fig. 3.The impact on the neutral-point voltage of load currents.

Suppose the three-phase loads are symmetrical, as shown in Fig. 3(a). When the big vector [PPN] operates, the three-phase loads are not connected with the neutral-point O. Thus, io is zero in this state, and the load currents have no effect on the neutral-point current. From Fig. 3(b), it can be seen that the flowing direction of ib cannot be determined when the medium vector [PON] operates. It can also be seen that the flowing direction of io is uncertain. Therefore, its influence on the neutral-point voltage cannot be determined. From Fig. 3(c), it can be seen that when the positive small vector [PP0] operates, io is equal to ic, and io flows into the neutral-point O. As a result, vo increases. When the negative small vectors operates in Fig. 3(d), it can be seen that io flows out of the neutral-point O. Therefore, vo decreases.

Comparing Fig. 3(c) with Fig. 3(d), it can be seen that when the positive small vector [PP0] and the negative small vector [00N] operates respectively, the flowing directions of io are opposite. As a result, their impact on vo is opposite. In addition, the neutral-point voltage unbalancing problem can be solved by properly selecting the operating time of the positive and negative small vectors.

IV. METHODS FOR SUPPRESSING THE LOW FREQUENCY OSCILLATION OF THE NEUTRAL-POINT VOLTAGE

A. Comparing the Conventional SPWM with the Proposed DPWM

The corresponding relationship between the three-phase modulation waves and the space vector distribution is shown in Fig. 4. When the modulation ratio is low, suppose that the three-phase modulation waves are in region I in Fig. 4(a). Thus, the reference voltage vector Vref falls in the small triangle area 1 of sector I as shown in Fig. 4(b).

Fig. 4.The relationship between the space vector and the three-phase modulation waves distribution.

Taking area 1 of sector I as an example, suppose the amplitude and period of the carrier wave are normalized using the conventional SPWM and the proposed DPWM controls. A detailed analysis is shown in Fig.5, which concerns the operating of the space vectors, and the corresponding neutral-point current.

Fig. 5.Space vector and neutral-point current.

From Fig. 5, it can be seen that the reference voltage vector is composed of three voltage vectors: V1[P00, 0NN], V2[PP0, 00N], and V3[000]. The vectors [P00] and [0NN] are a pair of positive and negative small vectors, so are the vectors [PP0] and [00N].

When using the conventional SPWM control method, as shown in Fig. 5(a), in a carrier cycle, the three voltage vectors above meet:

Where ds1+, ds1-, ds2-, ds3 is the operating time of vectors [P00], [0NN], [00N], and [000], respectively.

The modulation process of the proposed DPWM control method is shown in Fig. 5(b). Define the prior carrier cycle as an odd carrier cycle, and the next adjacent carrier cycle becomes an even carrier cycle. The details of the proposed DPWM control method are as follows:

(1) In the odd carrier cycle, the carrier cycle is divided into two equal parts: the prior and the latter half cycle. In the prior half cycle, the three-phase modulation waves va, vb, vc are all superimposed by an offset value Voffset, where Voffset = -Vmax, ( Vmax > 0), and Vmax=max{ va, vb, vc }. As a result, va’= va+Voffset, vb’= vv+Voffset, and vc’= vc+Voffset, where va’, vb’, vc’ represent the modulation waves with the proposed DPWM control. For the phase with the maximum instantaneous output voltage, its output leg voltage is clamped at the “0” level. In the latter half cycle, va, vb, vc are all superimposed by an offset value Voffset, where Voffset = -Vmin, ( Vmin < 0), and Vmin=min{ va, vb, vc }. Thus, for the phase with the minimum instantaneous output voltage, its output leg voltage is clamped at “0” level.

(2) In the even carrier cycle, the carrier cycle is also divided into two equal parts: the prior and the latter half cycle. In the prior half cycle, va, vb, vc are all superimposed by an offset value Voffset, where Voffset = -Vmin. Therefore, for the phase with the minimum instantaneous output voltage, its output leg voltage is clamped at the “0” level. In the latter half cycle, va, vb, vc are all superimposed by an offset value Voffset, where Voffset = -Vmax. Thus, for the phase with the maximum instantaneous output voltage, its output leg voltage is clamped at the “0” level.

Where va, vb, vc represent the modulation waves with the conventional SPWM control, and va’, vb’, vc’ represent the modulation waves with the proposed DPWM control. In addition, ds1+, ds1-, ds2-, ds3 is the operating time of vectors [P00], [0NN], [00N], [000], respectively, when using the conventional SPWM control.

From Fig. 5(a) and 5(b), the operating time of the positive and negative small vectors in the proposed DPWM and conventional SPWM control methods can be seen clearly. A performance comparison of the two methods is shown in Table II.

TABLE IIPERFORMANCE COMPARISON BETWEEN THE PROPOSED DPWM AND THE SPWM METHOD

From Table II, it can be seen that when using the conventional SPWM control method, the operating time of the vectors [PP0] and [00N] is 0 and ds2-, respectively, and that the operating time of vectors [P00] and [0NN] is ds1+ and ds1- respectively. The operating time of the positive and negative small vectors in pairs is not equal in a carrier cycle, and the neutral-point voltage unbalancing problem exists. When using the proposed DPWM control method proposed in this paper, it can be seen that the operating time of the vectors [PP0] and [00N] are both ds2-/2, and that the operating time of the vectors [P00] and [0NN] are both (ds1++ds1-)/2. Therefore, the operating time of the positive small vectors is equal to that of the negative small vectors in a carrier cycle.

According to the analysis above, the proposed DPWM control method distinguishes the odd and even carrier cycles. In addition, one carrier cycle is divided into two parts, which are controlled respectively. The operating time of the positive (or negative) small vector in the prior half cycle is equal to that of the negative (or positive) small vector in the latter half cycle. The average value of the neutral-point current is zero in a carrier cycle, and the neural-point voltage balance without a low frequency oscillation can be achieved.

B. Suppressing the Low Frequency Oscillation of the Neutral-Point Voltage

As shown in Fig. 1, when the neutral-point voltage is balancing, the voltages of C1 and C2 are both half the DC bus voltage. Under this condition, the neutral-point O is defined as the reference zero potential. ΔVNP is the voltage variation of the neutral-point O, which is relative to the reference zero potential, which is simply the neutral-point voltage variation. Thererore, the neutral-point voltage variation ΔVNP can be expressed as:

Where vc1 and vc2 represent the voltage of the capacitors C1 and C2, C is the capacitance of C1 and C2, and i1 and i2 represents the currents flowing through C1 and C2, respectively.

As a result, when the neutral-point voltage is balancing, ΔVNP is zero. Conversely, the voltages of C1 and C2 are not equal, and ΔVNP cannot be zero.

Suppose that the average value of the neutral-point current is equal to its instantaneous value in a carrier cycle. Then, the instantaneous value of the neutral-point current io(t) can be approximately expressed as:

Where io is the average value of the neutral-point current in a carrier cycle.

According to (2) and (3), in a carrier cycle, the relationship between ΔVNP and io can be derived as:

Where Ts is the period of a carrier cycle.

Using the conventional SPWM control, the neutral-point voltage fluctuates in a low frequency, which is mainly three times the line frequency. This has been analyzed in many literatures [9], [10].

In order to analyze the detailed realization of the proposed DPWM control method in this paper, which can suppress the low frequency oscillation of the neutral-point voltage, a line cycle is discretized to 400 carrier cycles, and the carrier frequency fs is 20kHZ. Since the proposed DPWM control method distinguishes the odd and even carrier cycles, and the prior and the latter half cycle in one carrier cycle, define half a carrier cycle as a unit, and k as an integer variable, k=0,1…799, so that the number of units in a line cycle is 800.

In a line cycle, the range is [0, 2π], and max(ωt) and min(ωt) and are defined as maximum and minimum instantaneous value of the three-phase sinusoidal waves, which are normalized. The envelop curve can be expressed as:

In order to ensure that the amplitude of the three-phase modulation waves with the proposed DPWM control method cannot exceed the amplitude of the triangular carrier wave, the following equation must be satisfied:

Derived from the above equation, m is expressed as:

Where m is the modulation ratio.

Thus, the proposed DPWM control method is applied to the three-level inverter at a low modulation ratio. In addition, its reference space voltage vector is only composed of positive small vectors, negative small vectors and the zero vector. Therefore, it is more effective to control the operating time of the positive and negative small vectors to be equal in a carrier cycle to suppress the low frequency oscillation and control the neutral-point voltage balancing.

When ωt is discretized, ωtk is used instead of ωt. Therefore, ωtk is defined as:

According to Fig. 5(b), the three-phase duty cycles are:

Supposing that m=0.3, the angular frequency ω=100π, and the load are purely resistive loads (cos(φ)=1). Therefore, the three-phase ideal duty cycles are shown in Fig. 6.

Fig. 6.Ideal duty cycles of proposed DPWM control.

The output currents of the NPC three-level inverter are:

Where φ is the load power factor angle, and Im is the amplitude of the three-phase output current.

From the analysis in section III, it can be seen that in a carrier cycle, the average value of the neutral-point current io can be expressed as:

Where ia(ωtk), ib(ωtk), and ic(ωtk) are the output currents of the NPC three-phase inverter, and da(ωtk), db(ωtk), and dc(ωtk) are the control duty cycles of the inverter.

Define the variable so that n= 0, 1 ... 399, and n is an integer, and the number of carrier cycles in a line cycle is 400. Therefore, supposing k= 2n, from (17), the neutral-point current of the prior and latter half cycles in a carrier cycle can be derived. Thus, the average value of the neutral-point current in a carrier cycle is as follows:

Where io(2n) and io(2n+1) are expressed as:

By substituting (18) into (4)，the expression of ΔVNP can be obtained as:

To compare with the conventional SPWM control, supposing m=0.3, φ=0 (under resistive load conditions), and when Im, C and Ts are normalized, the variation trend of io and ΔVNP with the conventional SPWM and proposed DPWM control methods are shown in Fig. 7.

Fig. 7.Curves of io and ΔVNP.

From Fig. 7(a), it can be seen that when using the conventional SPWM control method, io and ΔVNP both fluctuate at three times the line frequency.

In Fig. 7(b), io and ΔVNP are both zero in any carrier cycle with the proposed DPWM control method.

According to (4), (21) and m= 0.3, with the conventional SPWM and proposed DPWM control methods, the surface of ΔVNP as the function of φ and ωt is plotted as shown in Fig. 8. It can be seen that when φ varies from –π to π, or when ωt varies from 0 to 2π, using the conventional SPWM control method in Fig. 8(a), ΔVNP fluctuates, so that the neutral-point voltage has a low frequency oscillation.

Fig. 8.Surface of ΔVNP as the function with φ and ωt.

From Fig. 8(b), it can be seen that when using the proposed DPWM control method, ΔVNP is not varied respect to φ and ωt. It can also be seen that ΔVNP=0 in a line cycle.

From the above comparison, it can be seen that at different load power factor conditions, the proposed DPWM control method achieves the neutral-point voltage balancing without a low frequency oscillation.

V. EXPERIMENTAL VERIFICATION

In order to verify the validity of the proposed DPWM control method, which suppresses the low frequency oscillation of the neutral-point voltage, a NPC three-level inverter prototype has been built and tested in the lab.

The specification of the prototype are as follows:

When Vdc=200V, and Pin=200W, the experimental waveforms of ΔVNP, VA, vao, and iao with the conventional SPWM control and proposed DPWM control methods are shown in Fig. 9, where ΔVNP represents the input DC bus neutral-point voltage variation, VA represents the leg voltage of phase a, vao represents the output phase voltage of phase a, and iao represents the output current of phase a.

Fig. 9.Experimental waveforms.

From Fig. 9, it can be seen that when compared with the conventional SPWM control method under different load power factor conditions, the ripple value of ΔVNP is obviously decreased with the proposed DPWM control method.

Fig. 10-11 show the THD analysis results of vao and iao with the conventional SPWM control and the proposed DPWM method in this paper, respectively. Where urms and irms represents the Root-Mean-Square(RMS) value of the output voltage and current respectively. By using the proposed DPWM method in this paper, the THD value of iao decreases from 3.20% to 2.26% at cos(φ)=1, as shown in Fig 10(b) and Fig 11(b). At cos(φ)=0.866, as shown in Fig 10(d) and Fig 11(d), the THD value of iao decreases from 2.89% to 2.41%. In addition, the THD value of vao is decreased at different load power factor conditions. Therefore, using the proposed DPWM control method in this paper, the output waveforms show obvious advantages in terms of the THD at different load power factor conditions when compared with the conventional SPWM methods.

Fig. 10.THD analysis with conventional SPWM control.

Fig. 11.THD analysis with proposed DPWM control.

At different resistive load conditions, when the input power varies, the ripple value of ΔVNP, the THD value of the output current and the efficiency curves are shown in Fig. 12-14. It can be seen that at various input powers, the proposed DPWM control method proposed in this paper achieves the low frequency oscillation suppression for the neutral-point voltage. When compared with the conventional SPWM, the quality of the output waveforms and the system efficiency are improved with the proposed DPWM control method.

Fig. 12.Measured THD.

Fig. 13.Measured neutral-point voltage ripple.

Fig. 14.Measured efficiency.

VI. CONCLUSION

Three-level inverters have many advantages, such as low voltage stress on the switching devices and low output harmonics. As a result, they are suitable for high voltage, and medium or high power applications. When using the conventional SPWM control method, the DC bus neutral-point voltage has a low frequency oscillation, the output current contains a lot of harmonics, and the efficiency of the inverter is relatively low, especially when the input voltage or the input power is higher. To solve this problem, a new DPWM control method is proposed in this paper, which suppresses the low frequency oscillation of the neutral-point voltage, reduces the output current harmonics, improves the quality of the output waveforms, and increases the system efficiency. In order to verify the validity of the proposed DPWM control method, experimental results are obtained based on a NPC three-level inverter prototype. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed method.