I. INTRODUCTION

The silicon carbide (SiC) MOSFET is a promising candidate for next generation power devices. It is featured by much higher blocking voltages, lower on-state resistance, higher switching speeds and higher thermal conductivity than conventional silicon (Si) devices [1]-[5]. In addition, a SiC MOSFET is capability of operation under higher density power conversion [6]. The switching frequency has been continuously pushed up to the megahertz range to reduce the size of the passive components [7], [8]. However, as the switching loss increases and the effects of parasitic elements on the switching performance become intensified, there is a further increase in the switching frequency. In order to take full advantage of a SiC MOSFET, it is necessary to estimate the switching loss and to analyze the effects of the parasitic elements on the switching performance of the SiC MOSFET for optimization.

Investigation into this issue can be classified into three categories. One way to study this is by measuring experimental switching waveforms [9]-[14]. Some device manufactures provide the switching energy dissipation in a datasheet by capturing the experimental switching waveforms in a double-pulse-test circuit. However, this method needs oscilloscope probes that have a sufficient bandwidth to insure the high fidelity of the switching waveforms, especially for testing high switching-speed devices [15], [16]. On the other hand, the experimental switching waveforms are impacted by the parasitic inductances of particular PCB traces and the characteristics of free-wheeling diodes. Therefore, switching loss based on different experimental platforms may be different. Not only that, this method only provides experimental switching waveforms under the influence of parasitic elements. It does not provide explanations of the influence mechanism of the parasitic elements through measurement results.

In [17]-[20], a method for making simulation models, such as pspice models or saber models, is presented. For SiC MOSFETs, Cree has published LTspice models with the parasitic inductances in the package. The simulation model can be combined with an external circuit including the parasitic inductances of the PCB traces to calculate the switching loss and to obtain the switching waveforms under the influence of the parasitic elements. However, like the experimental method, this simulation method does not give the influence mechanism.

Analytical models are set up based on the mathematical methods in [21]-[30]. The piecewise linear model is the most simple and popular analytical model [21], [22]. However, the parasitic inductances and junction capacitances are not taken into consideration. In [32] and [33], it is shown that the nonlinear junction capacitances of power devices are critical for the switching transition. As a result they should be fully considered in the modeling and switching transient analysis, especially for high-frequency applications. In addition, the parasitic inductances are also very significant for the switching transient analysis in high-frequency applications [23]. Therefore, the results of the piecewise linear model cannot match well with the experimental results. In [23]-[30], analytical models considering the parasitic inductances and junction capacitances are presented. The equivalent circuits for each switching transition can be derived and solved. Then, the switching waveforms and switching loss can be calculated, and the effects of the parasitic elements on the switching performance can be analyzed. Some analytical models are designed to predict the switching performance of low-voltage MOSFETs [24]-[29]. The switching processes of a SiC MOSFET, which is a high voltage device, are different from the low-voltage devices usually operating at voltages lower than 40V. The drain-source voltage vDS of low-voltage devices drops to 0V before the drain current iD reaches Io during the turn-on transition, and iD can reach 0A before vDS reaches VDC during the turn-off transition [25], [31]. In general, these conditions will not happen to high voltage devices. The analytical models from [23] and [30] are for high voltage devices. In [23] and [30], the junction capacitances and trans-conductance are treated as constants, and the nonlinearity of these two elements is not considered. Therefore, these analytical models are also imprecise. In [30], the common source parasitic inductance is not considered, which is shared by the power loop and the gate loop. It plays a different role with the power loop parasitic inductances. In addition, [31] shows that the switching loss of a Cascode GaN HEMT, which are derived from terminal waveforms based on experiments, are imprecise. This is due to the fact that the energy in the junction capacitances is not dealt with well. However, this issue is not addressed or analyzed in any of the studies concerning SiC MOSFETs.

The objective of this paper is to estimate the switching loss and analyze the effects of the parasitic elements on the switching performance of a SiC MOSFET with an improved analytical model. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of trans-conductance. The switching processes are illustrated in detail, and the equivalent circuits are derived and solved during the switching transition. This paper is organized as follows. The proposed analytical model is established in Section II. Verification of the proposed analytical model of a SiC MOSFET is in Section III. The effects of the parasitic elements on the switching performance of a SiC MOSFET are illustrated in Section IV. Some conclusions are given in Section V.

 

II. ANALYSIS OF SWITCHING PROCESSES

To analyze the switching processes of a SiC MOSFET, a double-pulse-test circuit is used as an example. The employed double-pulse-test circuit considering the parasitic elements is shown in Fig. 1. The input voltage source VDC is constant, and the output current Io is constant. The parasitic elements in the package of the SiC MOSFET Q1 are the gate-source capacitance CGS, the gate-drain capacitance CGD, the drain-source capacitance CDS, the gate inductance LG1, the drain inductance LD1, the source inductance LS1, and the internal gate drive resistance RG1. The parasitic elements in the package of the freewheeling diode D are the junction capacitance CF, the cathode inductance LC1, the anode inductance LA1, and the on-state resistance RF. A SiC JBS diode is employed as the freewheeling diode, which does not have the reverse recovery charge Qrr. LC2, LA2, LG2, LD2, LS2, and LS3 represent the interconnection parasitic inductances of the PCB traces. In all of the parasitic inductances, LS1 and LS2 are the common source inductances shared by the power loop and the gate drive loop. RG2 represents the external gate drive resistance. The gate signal vP flips between VSS and VGS, and VSS is a negative value. The circuit in Fig. 1 is also suitable for analyzing the device performance during the switching transitions for other bridge configuration-based topologies, such as boost, buck-boost, half bridge, and full bridge.

Fig. 1.Double-pulse-test circuit considering parasitic elements.

A. Turn-on Switching Transition

Before Q1 is turned on, the output current Io flows through D, and the input voltage source VDC is applied to Q1. The turn-on switching transition can be divided into four stages, which are analyzed as follows. The complete switching waveforms are shown in the next section.

1) Stage 1, Turn-on Delay Time: When VGS is applied, the gate current iG charges CGS and CGD. CGS is much larger than CGD. Thus, the majority of the gate current charges CGS. Since the gate-source voltage vGS does not reach the threshold voltage Vth, Q1 is cut-off and almost no drain current flows into Q1. The equivalent circuit of this stage is shown in Fig. 2(a). During this stage, the circuit equations can be expressed as:

where RG=RG1+RG2, LG=LG1+LG2, and LCS=LS1+LS2. The gate-source voltage vGS can be solved by the iterative method presented concretely in the next stage, and the coefficient matrixes are shown in Appendix.

Fig. 2.Equivalent circuits for the turn-on transition. (a) Stage 1. (b) Stage 2. (c) Stage 3. (d) Stage 4.

This stage ends when vGS reaches Vth. Since Q1 is not activated, there is no switching loss during this stage.

2) Stage 2, Current Rising Time: When vGS reaches Vth, the channel of Q1 conducts, and the channel current iCH, which is controlled by vGS, increases. During this stage, Io transfers from D to Q1. The rising drain current iD and the falling forward current iF induce voltage drops across the parasitic inductances. This leads to CGD and CDS discharging through the channel of Q1, and the drain-source voltage vDS falling. The equivalent circuit is shown in Fig. 2(b), where Q1 is modelled as a dependent current source controlled by vGS. The expression of this source is given by:

where gf is the trans-conductance of Q1. The circuit equations can be expressed as:

where LP is the sum of the power loop parasitic inductances, LP=LC1+LC2+LA1+LA2+LD1+LD2+LS1+LS2+LS3, and VF is the forward voltage of D.

Since there are four independent state variables in Equs. (4)-(8), it is difficult to derive the time domain solutions without simplification. In order to enhance the accuracy of this analytical model, the iterative method is employed. Equs. (4)-(8) are transformed into:

where X=[iG vGS iD vDS vF]T, and A and B are the coefficient matrixes, which are shown in the Appendix. Afterwards, Equs. (4)–(8) can be solved according to the following formula:

where n=1, 2, 3…, and Δt is the calculation time step. All of the variables can be solved as Equ. (10).

This stage ends when the drain current iD reaches Io. During this stage, the channel of Q1 conducts, and a portion of the energy stored in CGD and CDS is dissipated through the channel. Therefore, the turn-on loss can be calculated as:

where, tn1 is the time of stage 1, and tn2 is the time of stage 1 and stage 2.

3) Stage 3, Voltage Falling Time: When iD reaches Io, D is able to block the voltage, Q1 need to assume Io, and the additional current is charging CF of the freewheeling diode. vDS eventually decreases and CGD and CDS continue to discharge through the channel of Q1. iD may have a ringing because of oscillations between LP and CF. The equivalent circuit is shown in Fig. 2(c), and the circuit equations different from stage 2 can be expressed as:

The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.

This stage ends when vDS decreases to iD·Ron, where Ron is the on-state resistance of Q1. At this point, the drain-source voltage and drain current transition are over. During this stage, the turn-on loss is the same as that of the previous stage, and it can be calculated as:

where tn3 is the time of stage 1, stage 2, and stage 3.

4) Stage 4, Gate Remaining Charging Time: Once vDS reaches iD·Ron, vGS continues to increase until it reaches VGS. The channel current iCH is no longer controlled by vGS, and ultimately goes back to Io. The equivalent circuit is shown in Fig. 2(d), where Q1 is modelled as the on-state resistance. The circuit equations different from stage 2 and stage 3 can be expressed as:

The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.

During this stage, the drain-source voltage and the drain current are almost steady. Therefore, there is no turn-on loss.

B. Turn-off Switching Transition

Before Q1 is turned off, the output current Io flows through Q1, and the input voltage source VDC is applied to D. The turn-off switching transition can be divided into four stages, which are analyzed as follows. The complete waveforms are shown in the next Section.

1) Stage 1, Turn-off Delay Time: When VSS is applied, CGS and CGD discharge, and vGS decreases. However, when Q1 is still in the on-state, Io keeps flowing through the channel of Q1. The equivalent circuit of this stage is shown in Fig. 3(a), and the circuit equations can be expressed as:

The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.

Fig. 3.Equivalent circuits for the turn-off transition (a) stage 1, (b) stage 2, (c) stage 3, and (d) stage 4.

This stage ends when vGS reaches Vmil, which is given as Equ. (17). During this stage, Q1 is still turned on. As a result, there is no turn-off loss.

2) Stage 2, Voltage Rising Time: During this stage, vDS increases, and iD charges CGD and CDS. iCH decreases because CGD and CDS need the charging current, and CF need to release energy. Therefore, vGS continues to decrease due to its dependent relation with iCH. The equivalent circuit is shown in Fig. 3(b), where Q1 is modelled as a dependent current source. The circuit equations can be expressed as:

The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.

This stage ends when the forward voltage vF of D decreases to –VF. Then, D is in the on-state. During this stage, the turn-off loss of Q1 can be calculated as:

where, tf1 is the time of stage 1, and tf2 is the time of stage 1 and stage 2.

3) Stage 3, Current Falling Time: During this stage, vGS and iCH decrease. vDS continues to increase, and CGD and CDS are charged. The rapidly changing currents iD and iF induce voltage drops across the parasitic inductances, which eventually incurs a voltage overshoot on vDS. The equivalent circuit is shown in Fig. 3(c), and the circuit equations different from stage 2 can be expressed as:

The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.

This stage ends when iCH reaches zero, and vGS reaches Vth. During this stage, the turn-off loss can be calculated as:

where, tf3 is the time of stage 1, stage 2, and stage 3.

4) Stage 4, Gate Remaining Discharging Time: When vGS drops below Vth, the channel of Q1 is totally shut down. Then vGS continues to decrease until it reaches Vss. During this stage, the drain-source voltage and the drain current have a ringing because the parasitic inductances oscillate with CGD and CDS. The equivalent circuit is shown in Fig. 3(d), and the circuit equations different from stage 2 and stage 3 can be expressed as:

The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix. As the ringing dissipation is very small and can be neglected, this stage has no turn-off loss.

 

III. VERIFICATION OF THE ANALYTICAL MODEL

In this part, experiments based on a double-pulse-test circuit are carried out to validate the proposed analytical model. In the double-pulse-test circuit, the device under examination is a 1200V SiC MOSFET C2M0080120D from CREE, Inc. The freewheeling diode is a 1200V SiC JBS diode C4D20120A with no reverse recovery charge. Note that the proposed analytical model is suitable for not only 1200V SiC MOSFETs from CREE, Inc., but for high voltage SiC MOSFETs from other companies as well.

A. Extraction of Key Parameters

In the proposed analytical model, the key parameters are the parasitic inductances, the junction capacitances and the trans-conductance, the accuracy of which influences the accuracy of the analytical model.

As packaging technology develops, LG1, LS1, and LD1 in the package of devices can be minimized to as low as the nH level. In addition, the extraction of the interconnection parasitic inductances of the PCB traces is implemented by an Ansoft Q3D Extractor finite-element analysis (FEA) simulation [34], [35]. Table I shows the parasitic inductances in the proposed analytical model.

TABLE IPARASITIC INDUCTANCES IN THE PROPOSED ANALYTICAL MODEL

The device manufacturer provides the curves of the input capacitance Ciss, the output capacitance Coss, and the reverse capacitance Crss in the datasheet. The relations between the capacitances given in the datasheet and the junction capacitances are Ciss=CGS+CGD, Coss=CGD+CDS, and Crss=CGD. Therefore, junction capacitances can be extracted from the datasheet. Obviously, Coss and Crss change with an applied voltage. According to [26], [32], and [33], the nonlinearity of the capacitance versus the voltage can be modelled as:

where k and λ are the two adjustment parameters extracted from the capacitance curves in the datasheet, v is the applied voltage, and C0 is the 0 V capacitance value.

Nevertheless, Equ. (27) cannot accurately fit the capacitance curves, especially the inflection point. Thus, the piecewise fitting method is employed for modelling. The values of Coss and Crss for the SiC MOSFET C2M0080120D can be expressed as Equs. (28)- (29).

Fig. 4 shows a comparison between the capacitance curves provided by the datasheet and the piecewise fitting. This figure shows that the capacitance curves under the piecewise fitting method match well with the datasheet. In addition, the junction capacitance CF of the freewheeling diode is also nonlinear, and it can be extracted based on the piecewise fitting method.

Fig. 4.Capacitance curves of SiC MOSFET C2M0080120D.

The device manufacture also provides the transconductance characteristic curve in the datasheet. The transconductance gf represents the incremental change of iCH over an incremental change of vGS. gf is also nonlinear and can be extracted according to the transconductance characteristic curve. The transconductance characteristic curve of a SiC MOSFET C2M0080120D can be expressed based on the piecewise fitting method. Fig. 5 shows a comparison between the transconductance characteristic curve provided by the datasheet and the piecewise fitting.

Fig. 5.Transconductance characteristic curve of SiC MOSFET C2M0080120D.

B. Verification

In this part, the experimental results of the drain current iD, the drain-source voltage vDS, and the switching loss p are recorded to compare with the analytical model. Fig. 6 shows the double-pulse-test hardware setup. Table II shows the critical test equipment for the experimental verification. Because of the high switching speed of the SiC MOSFET, the probes should have sufficient bandwidth to capture the fast rising and falling edges of the switching waveforms with high fidelity. As stated in [36] and [37], the equivalent frequency of a rising/falling edge can be approximated as:

where tr is the rising time of the switching waveform, and tf is the falling time of the switching waveform. In this experiment, the rising/falling edge of the captured waveform may less than 25ns. Therefore, the equivalent frequency is more than 10MHz. For the sake of accuracy, the bandwidth of the test equipment should be higher than ten times the equivalent frequency of the measured waveform [36], [37]. The test equipment shown in Table II meets this bandwidth requirement. Table III shows the initial parameters of the proposed analytical model.

Fig. 6.Double-pulse-test hardware setup.

TABLE IICRITICAL TEST EQUIPMENT FOR EXPERIMENTAL VERIFICATION

TABLE IIIINITIAL PARAMETERS OF THE PROPOSED ANALYTICAL MODEL

Fig. 7 shows comparisons between the switching waveforms provided by the experiment, the proposed analytical model, the analytical model in [23], and the analytical model in [30]. Table IV shows a switching time comparison during the switching transition. It is apparent that the proposed analytical model matches better with the experimental results (in terms of the voltage slope, the current slope, the voltage spike, and the current spike) than analytical models in [23] and [30]. It is easy to see that the oscillation frequency and oscillation amplitude in the voltage and current provided by the proposed analytical model are different from those of the experimental results. This is because the junction capacitances and trans-conductance of all the devices are difficult to maintain a high consistency with the data in the datasheet. In addition, the parasitic inductances include the self-inductances and the mutual-inductances, which are influenced by several factors, including the conductor position, current direction, and oscillation frequency [34], [35]. However, the current directions and oscillation frequency are difficult to predict accurately when conducting a FEA simulation.

Fig. 7.Switching waveforms of SiC MOSFET C2M0080120D provided by the experiment, the proposed analytical model, the analytical model in [23] and the analytical model in [30] (a) turn-on waveforms, and (b) turn-off waveforms. (Remark: According to the datasheet of SiC MOSFET C2M0080120D, in the analytical model in [23] and [30], the transconductance gf is set 9.8, and the junction capacitances are set as follows, CGD=100pF and CDS=300pF when vGS>Vth and vDSVth and vDS> vGS-Vth. And LCS is set 0nH in the analytical model in [30])

TABLE IVSWITCHING TIME COMPARISON DURING SWITCHING TRANSITION

The turn-on loss and the turn-off loss are shown in Fig. 8. The switching loss calculated based on experimental switching waveforms by integrating iD and vDS is called pe. The switching loss calculated based on the proposed analytical model by integrating iD and vDS is called pm1. The switching loss calculated based on the proposed analytical model by integrating iCH and vDS is called pm2. As shown in Fig. 8(a), pm2 is more than the other calculated results. This is due to the fact that the energy stored in CGD and CDS is dissipated by the channel during the turn-on transition, which is ignored by pe and pm1. As shown in Fig. 8(b), pm2 is less than the other calculated results. This is due to the fact that some of iD charges CGD and CDS during the turn-off transition, and the energy stored in the junction capacitances is embraced by pe and pm1.

Fig. 8.Switching loss of SiC MOSFET C2M0080120D provided by the experiment and the proposed analytical model (a) turn-on loss, and (b) turn-off loss.

 

IV. EFFECTS OF PARASITIC ELEMENTS ON THE SWITCHING PERFORMANCE

The switching processes of a SiC MOSFET are modeled in detail, and the proposed analytical model is verified effectively in the previous section. Therefore, the effects of the parasitic elements on the switching performance can be predicted according to the proposed analytical model. The effects of the gate drive resistance RG, the gate inductance LG, the common source inductance LCS, and the power loop inductance LP are analyzed. These parasitic elements can be changed within reasonable ranges of the actual conditions. Nevertheless, the effects of the junction capacitances are not analyzed because they are in the package of device and cannot be changed. In order to interpret the effects of the parasitic elements directly by sensors, the switching waveforms of the proposed analytical model with varied parasitic elements are plotted. It should be noted that one parameter is studied, while the other parameters are keep invariable and at their initial values.

A. Gate Drive Resistance RG

The switching waveforms of the proposed analytical model with varied values of RG are shown in Fig. 9. With a large RG, the switching speed is slowed down. The voltage stress is the voltage drops across the parasitic inductances induced by the falling current, and the current stress is caused by the charging current of CF of the freewheeling diode, which is related to the current slew rate and the parasitic inductances. Therefore, the device stress is reduced with an increasing RG. The switching loss is positively correlated to the switching time and the values of the voltage and current. In addition, it is negatively correlated to the switching speed. The increase in RG leads to an increase in the switching loss. The turn-on loss is due to the increase in the switching time, the decrease in the voltage and current slew rates, and the decrease in the voltage drops across the parasitic inductances. The turn-off loss is due to the increase in the switching time and the decrease in the voltage and current slew rates which outweigh the reduction of the voltage and current stresses.

Fig. 9.Switching waveforms of the proposed analytical model with varied RG (a) turn-on waveforms, and (b) turn-off waveforms.

B. Gate Inductance LG

The switching waveforms of the proposed analytical model with varied values of LG are shown in Fig. 10. It can be seen that they almost overlap. This proves that LG has little effect on the switching speed, device stress, and switching loss. In fact, according to the circuit design guidelines, LG should be kept small to minimize the oscillations in the gate drive circuit.

Fig. 10.Switching waveforms of the proposed analytical model with varied LG (a) turn-on waveforms, and (b) turn-off waveform.

C. Common Source Inductance LCS

The switching waveforms of the proposed analytical model with varied values of LCS are shown in Fig. 11. LCS is the sum of the common source inductances LS1 and LS2. This shows that a large LCS can reduce the current slew rate. However, the effect on the voltage slew rate is inconspicuous. LCS is shared by the power loop and the gate drive loop. In addition, the changing current will generate the voltage drop across LCS opposing real intention of the gate drive stage. Therefore, the effect of LCS on the current slew rate is similar to RG. According to Fig. 11, LCS decreases the device stress by reducing the current slew rate. The switching loss increases with LCS. This is due to the same reason as RG.

Fig. 11.Switching waveforms of the proposed analytical model with varied LCS (a) turn-on waveforms, and (b) turn-off waveforms.

D. Power Loop Inductance LP

LP lumps all of the parasitic inductances (LC1, LC2, LA1, LA2, LS1, LS2, LS3, LD1, and LD2) along the power loop. The switching waveforms of the proposed analytical model with varied values of LP are shown in Fig. 12. The effect of LP on the switching speed is similar to LCS, which has been given. However, the effect of LP on the device stress is opposite to LCS. LP increases the device stress so that the increase in LP outweighs the reduction in the current slew rate. The turn-on loss decreases with an increasing LP, because the decrease in voltage drops across the parasitic inductances outweighs the other factors. The turn-off loss increases with a large LP due to the decrease in the current slew rate and the increase in the voltage stress.

Fig. 12.Switching waveforms of the proposed analytical model with varied LP (a) turn-on waveforms, and (b) turn-off waveforms.

E. Summary

Based on the preceding discussion, the effects of the parasitic elements on the switching performance can be summarized as follows.

With respect to the switching speed, an increase in RG can slow down the switching speed. LCS or LP can slow down the current slew rate. However, they have little effect on the voltage slew rate. Regarding to the device stress, RG and LCS can reduce the device stress. However, LP has the opposite reaction. For the switching loss, RG and LCS can add to the switching loss. Nevertheless, LP decreases the turn-on loss and increases the turn-off loss.

Note that LG has little effect on the switching speed, device stress and switching loss. However, LG may cause oscillations in the gate drive circuit.

After a comprehensive assessment of the effects of the parasitic elements, when initially proceeding the PCB circuit design, LCS should be minimized to get a low switching loss, LP should be minimized to get a low device stress and a low turn-off loss, and RG should be chosen at a reasonable value to mitigate the conflict between the switching loss and the device stress.

 

V. CONCLUSION

This paper presents an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of a SiC MOSFET. The proposed analytical model takes the parasitic inductances, the nonlinearity of the junction capacitances, and the nonlinearity of the trans-conductance into account. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. The proposed analytical model with varied parasitic elements is compared to account for the effects of parasitic elements on the switching performance of a SiC MOSFET.

In this paper, the following points should be noted:

1): The switching loss calculated based on an experiment is imprecise. The experimental results neglect the energy released by CGD and CDS during the turn-on transition and embrace the energy stored in CGD and CDS during the turn-off transition.

2): When initially proceeding with the PCB circuit design, LCS should be minimized to get a low switching loss, LP should be minimized to get a low device stress and a low turn-off loss, and RG can be chosen to achieve a better compromise between the device stress and the switching loss.