I. INTRODUCTION

Synchronous rectification is widely applied in low-voltage converters to improve power conversion efficiency. In the synchronous converters, a power switch with on-resistances in order of milliohms, namely, synchronous rectifier (SR) switch, is used instead of a diode. Thus, conduction losses are reduced given that the forward voltage drop of the diodes is noticeable at low-output voltages [1]-[3]. The main drawback of the synchronous converters is the reverse recovery losses of the low-speed SR switch body diode. Before the main switch turns on instantly, the SR switch is turned off and its body diode conducts for a short time. Hence, the reverse recovery time of the SR switch body diode occurs when the main switch is turned on, thereby causing a large current spike in the main switch [4]. This problem significantly contributes in increasing switching losses and EMI. The high-frequency power conversion is also limited. However, high-operating frequency is desirable to achieve high power density by reducing the converter reactive components size [5], [6]. Soft-switching techniques are employed to resolve these problems.

Among the soft-switching techniques, zero-voltage-transition (ZVT) technique is widely used in many converters because of common features, such as low circulating current, retaining PWM operation, and wide load soft-switching range [7]-[10]. In general, ZVT technique provides zero-current switching (ZCS) condition for the converter main diode at turn-off and zero-voltage switching (ZVS) condition for the main switch through an additional auxiliary switch and some passive elements. Consequently, ZVT technique decreases the switching losses and EMI. The reverse recovery losses of the SR switch body diode losses can also be reduced significantly by applying ZVT techniques to the synchronous converters. In [1], [2], [11]-[13], ZVT technique is applied to the synchronous converters to improve efficiency and to overcome the SR reverse recovery problem. However, the converter of [11] suffers from numerous auxiliary elements. In [11], [12], the voltage stress on the auxiliary switch is equal to or higher than the main switch voltage stress. Given that the auxiliary switch in ZVT converters is turned on under ZCS condition, increased voltage stress results in increased capacitive turn-on losses. In conventional power switches, low-voltage switches also benefit from the low value of on-resistance RD(on), thereby resulting in low conduction losses. In the ZVT synchronous converters of [1], [2], [13], the voltage stress on the auxiliary switch is reduced to approximately half of the main switch voltage stress. The reverse recovery losses of the SR switch body diode are totally eliminated. However, the auxiliary switch in [1], [2], [11]-[13] needs a floating gate drive because the source terminal of the auxiliary switch is not in common with the input voltage source ground, thereby resulting in complexity of the gate drive circuit. The other ZVT technique is applied in [14]-[18] where coupled inductors are used. In [14]-[17], the auxiliary inductor is coupled with the main converter inductor, and the leakage inductor is used as the resonance inductor. Thus, all converter inductors are implemented on a single core, thereby resulting in significant reduction of the converter size. However, using a coupled inductor in [14]-[17] results in increased auxiliary switch voltage stress. In [17], the auxiliary switch is also turned off under a hard switching condition. In [18], a separate core is needed for the coupled inductor, thereby resulting in too many auxiliary elements. The auxiliary switch in [14]-[18] needs floating gate drive circuit.

In this study, a new family of nonisolated synchronous converter is introduced. In the proposed converters, the advantages of the ZVT converters of [13]-[17] are achieved. The SR diode reverse recovery losses are completely eliminated by applying the idea of [13], and soft switching condition is provided for the whole converter operating region without any extra voltage and current stresses on the main and SR switches. In this study, the analytical work is conducted to design properly the converter for the whole converter operation region. The auxiliary inductor is also coupled with the main converter inductor. All the converter inductors are also implemented on a single core with the leakage inductor as the resonance inductor. In addition to these advantages, the voltage stress of the auxiliary switches, compared with the previously proposed ZVT converters, is reduced significantly, and the auxiliary switches do not need the floating gate drive circuit. Thus, low-voltage power switches with ultralow on-resistance (RD(on)) are used. The turn-on capacitive losses of the auxiliary switch are also reduced.

The analysis and operation of the proposed ZVT synchronous buck converter are described in Section II. The design considerations and a design example are presented in Sections III and IV, respectively. The experimental results are shown in Section V to confirm the theoretical analysis. Finally, the auxiliary circuit is developed for the other nonisolated synchronous converters, as discussed in Section VI.

II. CIRCUIT DESCRIPTION AND OPERATION

The proposed ZVT synchronous buck converter is shown in Fig. 1(a). The main converter is composed of main switch Sm, SR switch SSR, output filter inductor L1 and output capacitor filter C. The auxiliary circuit is composed of auxiliary switch Sa, rectifying diode Da, and inductor L2, which is coupled with the main inductor L1. The turn ratio of the coupled inductors L1 and L2 is n (L2 = n2 L1). The auxiliary switch source terminal agrees with the input voltage source ground. Hence, the auxiliary circuit does not need the floating gate drive. Fig. 1(b) illustrates that the coupled inductors can be modeled as a combination of an ideal transformer with a corresponding turn ratio (n), magnetizing inductance (LM), and a leakage inductance (Llk). The magnetizing inductances LM and Llk are employed as the converter main inductor and resonance inductor, respectively. The converter has eight operating modes in a switching cycle. The equivalent circuits of each operating mode are shown in Fig. 2, where the current arrows refer to the actual direction of the current. The key waveforms of the converter are illustrated in Fig. 3. All elements are assumed ideal to simplify the converter analysis. The magnetizing inductor current and input voltage are also assumed constant in a switching cycle and equal to ILM and Vin, respectively.

Fig. 1.Proposed ZVT synchronous buck converter and its equivalent circuit. (a) Proposed converter. (b) Equivalent circuit.

Fig. 2.Equivalent circuit for each operating mode of the proposed converter.

Fig. 3.Converter theoretical waveforms.

Prior to the first mode, SSR is presumably conducting the magnetizing inductor current (ILM), and all other semiconductor devices are off. No current presumably flows in the windings of the ideal transformer in the model. The voltages across the primary (Vp) and secondary (Vs) windings are Vo and nVo, respectively.

Mode 1: (t0 − t1) This mode starts by turning the auxiliary switch Sa on. Thus, the secondary winding voltage of the ideal transformer (nVo) placed across Llk and Sa current starts to increase linearly as follows:

Given the series inductor Llk, Sa is turned on under ZCS condition. During this mode, ISa enters the dotted terminal of the ideal transformer secondary windings. Thus, nISa flows out of the dotted terminal of the primary side. Therefore, SSR current equation is

In this mode, SSR current decreases from ILM to zero and then increases in the opposite direction for a short time through the SSR. At the end of this mode, SSR current is defined as -IRev. Consequently, Sa current is (ILM + IRev) / n. The SSR current is reduced through the SR switch SSR. Hence, the reverse recovery of the SSR body diode is prevented from occurring, and the diode reverse recovery losses are eliminated completely. The duration of this mode is

The value of IRev is effective in providing ZVS condition when the converter operates in operating duty cycles below 0.5. This point is discussed in the design consideration section.

Mode 2: (t1 − t2) In this mode, the SR switch SSR is turned off, and a resonance starts between Llk and CS. Given the capacitor CS, SSR is turned off under ZVS condition. During this resonance, CS discharges from Vin to zero to provide ZVS condition for Sm at turn-on. Sm voltage is

where

At the end of this mode, Sa current is I0.

Mode 3: (t2 − t3) At t2, the Sm body diode starts to conduct. Thus, the main switch Sm can be turned on under ZVS condition. In this mode, the voltage across the primary and secondary windings of the ideal transformer in the model are changed to −(Vin - Vo) and −n(Vin - Vo), respectively. Therefore, the negative voltage placed across Llk and Sa currents starts to reduce linearly as follows:

Consequently, Sm current is

At the end of this mode, ISm and ISa currents reach zero and ILM/n, respectively. The body diode of Sm is turned off under ZCS condition. The duration of this interval is

Mode 4: (t3 − t4) In this mode, Sa current reduces from ILM/n to zero, and the rectifying diode Da prevents the Sa current to follow in the opposite direction. Thus, the auxiliary switch of Sa can be turned off under ZCS condition. ISm increases from zero to ILM. Sa and Sm current equations are as follows:

The duration of this mode is

Mode 5: (t4 − t5) In this mode, no current exists in the auxiliary circuit, and ILM flows through the Sm. This mode is identical to a conventional PWM buck converter when the main switch is on and the main converter inductor (LM) stores energy.

Mode 6: (t5 − t6) At t5, the main switch Sm is turned off under ZVS condition because of the capacitor CS. CS is charged linearly by the magnetizing inductor current ILM through turning Sm off. At the end of this mode, Cs is charged to Vin, and the SSR body diode begins to conduct.

Mode 7: (t6 − t7) This operating mode is identical to a conventional PWM buck converter when the main switch is off and the stored energy in LM flows to the output through the SSR body diode.

Mode 8: (t7 − t0 + T) The SR switch SSR can be turned on under ZVS condition by conducting the SSR body diode. Thus, ILM flows to the output through SSR.

III. DESIGN CONSIDERATIONS

The main synchronous buck converter is designed similar to a regular PWM buck converter. In the proposed converter, LM is employed as the converter filter inductor. Thus, it is designed as the inductor filter in a conventional PWM buck converter.

As discussed in the previous section, in mode 1, the current of the SR switch is reduced to zero by the auxiliary circuit to eliminate the rectifying diode reverse recovery losses. This current also flows in the opposite direction for a short period. The final opposite current value of the SR switch is defined as IRev. Thus, reverse recovery losses are eliminated completely if IRev is equal or greater than zero. By contrast, the main switch voltage must be zero at the end of the operating mode 2 to achieve the ZVS condition for the main switches at turn-on. Thus, the following equation should be satisfied from Equ. (4):

In the buck converter, Vo = VinD. Thus, Equation (12) is written as follows:

Equ. (13) shows that the value of IRev is effective in ZVS condition. The required value of IRev to achieve ZVS condition is defined as IRev_Req. According to Equ. (13), the normalized value of IRev_Req versus D is plotted in Fig. 4 [7]. Consequently, the ZVS condition of the main switch at turn-on and the elimination of the rectifying diode reverse recovery are provided simultaneously if the value of IRev is greater than IRev_Req. Thus, the following soft switching condition can be formulated:

IRev, which satisfies the preceding condition, must be provided. IRev value is obtained from Equ. (3) as follows:

where (t1 − t0) is mode 1 duration time. Given that this time is the duration time between the auxiliary switch turn-on and the SR switch turn-off, adjusting this duration is feasible.

Thus, the following soft switching condition is achieved from Equs. (14) and (15):

where ΔTdelay is the duration time between the auxiliary switch turn-on and the SR switch turn-off. Consequently, the ZVS condition of the main switch at turn-on and the elimination of the rectifying diode reverse recovery are provided by tuning ΔTdelay as formulated in Equ. (16). In Equ. (16), IRev_Req should be extracted for the minimum value of the duty cycle. Equ. (16) indicates that ΔTdelay value depends on the value of the main inductor current ILM. In this case, a feedback of the converter current value and a variable delay circuit are essential. In a conventional PWM current mode controller, the current feedback of the converter current value is available. However, the value of ΔTdelay can be adjusted for the full load condition when the value of ILM is at the maximum value to avoid complexity. Thus, the current feedback is not necessary, and a simple fixed value delay circuit can be applied. Additional circulating current at light loads can be obtained by applying the fixed value of ΔTdelay.

Fig. 4.Normalized value of IRev_Req versus D.

The turn-on period of the auxiliary switch Ton_aux should be sufficient, in which the auxiliary switch current can be reduced to zero, to achieve the ZCS condition for the auxiliary switch at turn-off. Thus, Ton_aux should be greater than the duration time of the operating modes 1, 2, 3, and 4. In this case, the duration time of mode 2 is estimated at one-quarter of the resonance period time, and the auxiliary switch current during mode 2 is assumed constant. Thus, the auxiliary switch turn-on period Ton_aux is obtained from Equs. (3), (5), (8), and (11) as follows:

Hence, the ZCS condition of the auxiliary switch at turn-off is provided by tuning Ton_aux as formulated in Equ. (17). ILM and Vin should be designed for the full load and minimum values of the input voltage, respectively, to achieve ZCS condition at the worst case operating condition. IRev_Req should be extracted for the minimum value of the duty cycle, and ω0 is obtained from Equ. (5).

Similar to other DC–DC PWM converters, the proposed converter employs the conventional controllers. The schematic of the interface circuit is presented in Fig. 5, where ΔTdelay and Ton_aux are obtained from

Fig. 5.Schematic of the interface circuit to adapt the output pulse of the PWM controller to the proposed converter.

Equs. (16) and (17), to adapt the output pulse of a conventional PWM controller to the proposed converter, and ΔTdead_time is the dead time between the conduction time of Sm and SSR when the snubber capacitor is discharged. This time is set to the following one-quarter resonance period to guarantee that the main switch turns on when the snubber capacitor is discharged completely:

The capacitor CS provides ZVS condition for the main and SR switches at turn-off instant. Therefore, its value can be selected similar to any snubber capacitor as follows [19]:

where tf is the switch current fall time, ISW is the switch current before turn-off, and VSW is the switch voltage after turn-off. Similarly, the inductor Llk provides ZCS condition for the auxiliary switch at turn-on instant. Its value can be selected according to [19] as follows:

where tr is the switch current rise time, ISW is the switch current after turn-on, and VSW is the switch voltage before turn-on. The obtained snubber values are the minimum values. In practice, the snubber values should be larger than the minimum values to guarantee soft switching. However, obtaining a large Llk results in long transient modes, as observed in Equ. (17). Thus, conduction losses and limitations exist in duty cycle. According to Equ. (17), the following condition should be satisfied

where T is the converter switching period.

Finally, the values of n must be selected. The voltage stress on the auxiliary switch is equal to nVo. Thus, a small selection of n results in small values of auxiliary switches voltage stress. However, a small value of n reduces Llk value, which serves as the snubber inductor for the auxiliary switches. The value of n can be selected in the range of 1/3 to 1/2.

IV. DESIGN EXAMPLE

A design example for the proposed converter is presented in this section. The design requirements are defined as follows:

• Output power (P) = 180 W;

• Input voltage (Vin) = 80 V;

• Output voltage (Vo) = 30 V;

• Operating frequency = 100 kHz.

A. Converter Component Selection

On the basis of the converter input data, the operating duty cycle (D) and the magnetizing inductor current (ILM) are obtained as follows:

ΔILM is selected as 2 A to ensure that the converter operates in continuous conduction mode at load variation above 20% of full load. Thus, the main converter inductor (LM) is designed as follows [19]:

The value of LM is selected as

As discussed in the previous section, the value n is selected as

Thus, the inductance of the secondary winding is obtained as

For the main and SR switches, IRF540 (VDS = 100 V, RD(on) = 44 mΩ, tf = 35 ns) is used. According to the converter input data and theoretical analysis, the auxiliary switch voltage stress is approximately 15 V (nVo). For the auxiliary switch (Sa), IRF1404 (VDS = 40 V, RD(on) = 4 mΩ, tr = 190 ns) is applied and BYV32 is used for the rectifying diode (Da).

The values of CS and Llk are designed from Equs. (19) and (20) as

The value of CS is selected as

The approximate value of Llk is obtained as

B. Auxiliary Switch Timing Design

On the basis of the selected components, the values of Z0 and ω0 are obtained from Equ. (5) as

According to the discussions in the previous section and from Fig. 4, for D = 0.375, the normalized value of IRev_Req is

Hence, the value of IRev_Req is

Thus, the values of ΔTdelay , Ton_aux, and ΔTdead_time are obtained from Equs. (16) to (18) as

These duration times are set at

As discussed in the previous section, the fixed value of ΔTdelay = 1 μs is applied to avoid complexity. Thus, the auxiliary circuit does not need the current feedback, and a simple fixed value delay circuit can be applied. On the basis of the selected component values, the condition of Equ. (21) is satisfied as follows:

Thus, the duration time of the transient modes is approximately 1.6 μs, which is lower than 20% of the converter switching period.

V. EXPERIMENTAL RESULTS

A prototype of the proposed converter is implemented for the input data and the designed components presented in the previous section to verify the principle of operation. As discussed in the previous section, the auxiliary switch voltage stress is approximately 15 V (nVo), which is approximately 20% of the main switch voltage stress. This point provides the use of a low-voltage power switch with low RD(On) for the auxiliary switch to reduce its conduction and capacitance turn-on losses. In the previous ZVT converters, the voltage stresses of the auxiliary switches compared with those of the main switch are approximately 120% in [14]-[16], 90% in [17], and 40% in [7], [13].

The experimental results at full load (180 W) and light load (35 W) are shown in Figs. 6 and 7, respectively. Before the main switch turn-on instant, the snubber capacitor is discharged completely. The ZVS condition at full load and light load is also provided for the main switch turn-on instant. This condition is achieved, given that ZVS at full load condition is the worst case scenario. The snubber capacitor provides ZVS condition for both main and SR switches at turn-off. No additional voltage stress exists on the main and SR switches voltage waveforms. The ZCS condition of the auxiliary switch is also achieved for both turn-on and turn-off instants.

Fig. 6.Experimental waveforms at full load (180 W): (top waveform) current and (bottom waveform) voltage of the (a) main switch Sm, (b) auxiliary switch Sa, and (c) SR switch SSR (time scale is 1 μs/div.)

Fig. 7.Experimental waveforms at light load (35 W): (top waveform) current and (bottom waveform) voltage of the (a) main switch Sm, (b) auxiliary switch Sa, and (c) SR switch SSR (time scale is 1 μs/div.)

The power loss at each component of the proposed converter in comparison to the regular hard switching converter and previously ZVT converters is presented in Table I to evaluate the power losses. The losses of all converters are estimated for a buck converter with the input data presented in the design example section. The average and root mean square values are extracted with the simulation results. Compared with the previous ZVT converters in [7], [17], [14]-[16], the proposed converter benefits from efficiency. In [7], a high-voltage switch with slow body diode should be applied as the SR switch, which increases the conduction losses, to achieve ZVS condition for the duty cycles below 0.5. In [17], hard switching of the auxiliary switch increases the losses. In [14]-[16], a power switch with high RD(on), which increases the conduction losses, should be applied because of the high-voltage stress of the auxiliary switch. Finally, unlike the converter in [13], the efficiency of the proposed converter is reduced by approximately 0.2%. However, compared with the converter in [13], the proposed converter benefits from a reduced volume caused by the implementation of all the converter inductors on a single core. Unlike the converters in [7], [13] and that of ZVT converters with coupled inductors in [17], [14]-[16], the gate drive circuit of the proposed converter is simple because the auxiliary switch does not need the floating gate drive circuit.

TABLE ICOMPARISON OF LOSSES IN THE PROPOSED CONVERTER, REGULAR HARD SWITCHING CONVERTER, AND PREVIOUS ZVT CONVERTERS

The converter efficiency curve is shown in Fig. 8. The efficiency of hard switching is for a regular synchronous buck converter with the same parameters with IRF540 as their switches.

Fig. 8.Efficiency comparison of the proposed soft switching converter with its hard switching counterpart.

VI. OTHER ZVT SYNCHRONOUS CONVERTERS WITH COUPLED INDUCTORS

Similar to the synchronous buck, this ZVT technique can be applied to other nonisolated synchronous converters to improve their efficiency, as shown in Fig. 9. In all topology variations, the auxiliary switch source terminal agrees with the input voltage source ground. For other topologies, the theoretical operating modes are similar to the operation of the synchronous buck converter explained in Section II. Thus, further explanation is not given.

Fig. 9.Other family members of the proposed converter: (a) boost, (b) buck/boost, (c) cuk, (d) SEPIC, and (e) Zeta.

VII. CONCLUSION

A family of ZVT synchronous converters is introduced. Theoretical analysis for a synchronous buck converter is presented in detail. The theoretical analysis shows that the ZVS condition of the main switch at turn-on and the elimination of the rectifying diode reverse recovery are provided by tuning the duration time between the auxiliary switch turn-on and the synchronous rectifier switch turn-off as formulated. The ZCS condition for the auxiliary switches at both turn-on and turn-off instants is achieved. Consequently, high efficiency over a wide operating range is obtained. In addition, the auxiliary switches benefit from low-voltage stress (nVo), and floating gate drive circuit is not necessary. To validate the theoretical analysis, a 180 W, 80 V to 30 V prototype of the converter at 100 kHz is implemented. The auxiliary voltage stress is approximately 20% of the main switch voltage stress. Other family members of the proposed converters are presented.