I. INTRODUCTION

Three-level DC-DC converters (TLDCs) have become a key issue in power electronics because of the rapidly increasing demand for high-input and high-efficiency isolated DC-DC power supplies [1], [2]. Interest in these devices stems from the research of Pinheiro and Barbi, who first introduced multilevel technology to the DC-DC power conversion field [1]. Five basic TLDCs were discussed and compared in [3], and most existing TLDCs are derived from these five topologies. A zero-voltage and zero-current switching (ZVZCS) TLDC was proposed in [4], in which a flying capacitor is used to assist zero-voltage switching (ZVS) of the leading switches, and an auxiliary secondary current reset circuit is added to assist in the zero-current switching (ZCS) of the lagging switches. Moreover, the converter in [4] can be switched in the phase shift (PS) mode, which makes this topology applicable. Many satisfactory contributions have been made to this topic. New TLDCs that have different useful features are proposed in [5]-[9]. Some good solutions that extend the soft switching load range of the primary switches were provided in [10]-[13]. A full bridge (FB) TLDC for wind turbines in a DC grid was investigated in [14]. Improved control strategies were discussed in [15] and [16]. All the references listed above have made the TLDCs applicable.

However, limitations still exist. In most TLDCs, the secondary rectified voltage is a two-level waveform. Large voltage ripple across the output filter requires a larger output inductor to smoothen the ripple current that flows through it, thereby increasing the overall system volume and slow down possible system dynamic responses [3], [17]-[21]. Furthermore, the input current is discontinuous, thereby requiring a large input filter to confirm the corresponding electromagnetic compatibility standards [3]. Several papers have been published to solve the abovementioned problems. A ZVZCS hybrid FB TLDC was proposed in [17], which can obtain a three-level (TL) secondary rectified voltage waveform before the output filter. In addition, two cutoff diodes are added to minimize the switching loss of the lagging switches [17]. A TL combined DC-DC converter (TLCDC) with six power switches was proposed in [18], which features even voltage stress on the primary devices and TL secondary rectified voltage waveform. The converter in [18] has good soft switching characteristics because it utilizes ZVZCS technology. In [19], an FB TLCDC was proposed, which can achieve a TL secondary rectified voltage waveform before the LC filter, as well as wide ZVS load range for all primary switches. A TLCDC with no added clamping device was discussed in [20]. To find a new topology with a simple and compact primary circuit, a TLCDC with four switches was proposed in [21], which has the minimum number of the primary switches among all TLCDCs. However, the main disadvantage of this converter is the limited output range with ZVS operation. During some abnormal situations, i.e., startup or overload/short circuit, the converter in [21] can only be switched in the hard switching mode to regulate the output voltage down to zero. Furthermore, the ZVS load range of the lagging switches in [21] is limited because only the energy stored in the leakage inductances can be used. Thus, a new TLDC characterized by a TL secondary rectified voltage waveform, simple and compact primary power circuit, good soft switching characteristics, and wide output range with soft switching operation must be found.

A diode-clamped TLDC with full ZVS load range, TL secondary rectified voltage waveform, and wide output range with soft switching operation is proposed in this paper. This paper is organized as follows: In Section II, the configuration and operation principle of the proposed converter are described. In Section III, important technical issues are discussed. In Section IV, experimental results are presented and discussed. In the last section, the main conclusions are given.

 

II. CONFIGURATION AND OPERATION PRINCIPLE

A. Configuration

Fig.1 shows the circuit of the proposed converter. The four primary switches are series connected, and the off-state voltage of these switches is clamped by Dcl1, Dcl2, Cin1, and Cin2. Cin1 and Cin2 are the input capacitors with the same value and share the input voltage evenly during the operation, i.e., VCin1= VCin2= Vin/2. Llk is the equivalent leakage inductance in the primary side of the transformer. Lm is the magnetizing inductance. The turn ratios in the proposed converter are set at NTp/NTs1= kT1andNTp/NTs2=kT2. Sse1 and Sse2 are the secondary switches. Do1–Do6 are the rectifier diodes, and the output filter is composed of Lo and Co. Ro is the load resistor.

Fig. 1.Proposed diode-clamped TLDC.

B. Normal Operation

Fig.2 depicts the key waveforms. Twelve operation stages are present during the entire switching cycle, and the operation stages in the first half-switching cycle are illustrated in Fig.3. Before the analysis, some assumptions are set to simplify the explanation: all the components in the topology are ideal; the voltage ripple on Cin1 and Cin2can be neglected; kT’= (kT1‧kT2) / (kT1+ kT2); and the output filter and load are replaced by a constant current source Io. The output capacitance of each primary switch is with the same value and represented as Cos in the following equations.

Fig. 2.Key waveforms of the proposed converter.

Fig. 3.Operation stages of the proposed converter: (a) stage 1, (b) stage 2, (c) stage 3, (d) stage 4, (e) stage 5, and (f) stage 6.

Stage 1 [Fig.3 (a)]: Before t0, the circuit is operated in a steady condition. The primary side powers the load. S1 and S2 are on; Do3 and Do6 are conducted; Sse2 is also on, but the current that flows through Sse2 is zero because Do2 is off. vBA=Vin/2, vrect=Vin/2kT2, ip= Io/kT2, iLlk equals the sum of ip and im, im increases with time linearly, and the slope is

Stage 2 [Fig.3 (b), t0–t1]: At the instant t0, Sse2 is turned off at zero-current. Primary side powers the load. vBA=Vin/2,vrect=Vin/2kT2, ip =Io/kT2, iLlk equals the sum of ip and im, and im keeps increasing.

Stage 3 [Fig.3 (c), t1–t2]: At the instant t1, Sse1 is turned on, Do1 is conducted, and Do3 is off. The primary side powers the load. vBA=Vin/2, vrect=Vin/2kT’, ip=Io/kT’, iLlk equals the sum of ip and im, and im linearly increases with time.

Stage 4 [Fig.3 (d), t2–t4]: At t2, S1and S2are simultaneously turned off at zero voltage because of the existence of C1 and C2; iLlk charges C1 and C2 and discharges C3 and C4 linearly with time. During this interval, the value of im can be treated as a constant value, which is represented by Im in the following equations. The voltage of point B decreases linearly with time before vrect is zero, and its value is

vBA is

vrect is defined as

Substituting Equ. (3) into (4) obtains

When vrect is zero, the voltage of point B can be calculated by Equs. (2) and (5), which is Vin/2. The time of this period is

After t3, the circuit will be operated in freewheeling mode. iLlk charges C1 and C2, and discharges C3 and C4 linearly with time. This stage ends until vC1=vC2= Vin/2, and vC3=vC4=0.

Stage 5 [Fig.3 (e), t4–t5]: At t4, D3 and D4conduct naturally. The circuit is maintained in freewheeling mode; iLlk decreases because negative voltage is applied to the terminals of Llk; during this stage, S3 and S4must be turned on to achieve ZVS. According to Fig.2, S3 and S4 are turned on at the instant t5.

Stage 6 [Fig.3 (f), t5–t6]: At t5, S3 and S4are switched on; ip increases in the inverse direction. When ip reaches -Io/kT2, the freewheeling mode is over. The primary side continuously powers the load. After t6, vBA=-Vin/2, vrect=-Vin/2kT2, ip=-Io/kT2, iLlk equals the sum of ip and im, im linearly decreases with time, and the slope is determined by Equ. (1). The current that flows through Sse1 is zero because Do1 is off. After stage 6, the circuit will be operated in the second half-switching cycle. As shown in Fig.3, during normal operation, the current that flows through Dcl1and Dcl2is zero, which means a lower current rating requirement of Dcl1and Dcl2.

TABLE IVOLTAGE STRESS ON THE SECONDARY POWER DEVICES

C. Soft Start Operation

Fig. 4 illustrates key waveforms during soft start operation, and the voltage stress on the secondary devices is provided in Table II. During soft start, Sse1 and Sse2 are off, and the proposed converter can be treated as a conventional diode-clamped TLDC in [1]. The operating principle for this procedure is not provided here for the sake of simplicity, and detailed information can be found in [1].

Fig. 4.Key waveforms during soft start operation.

TABLE IIVOLTAGE STRESS ON THE SECONDARY POWER DEVICES

 

III. TECHNICAL ANALYSIS

A. ZVS of Primary Switches

During the operation, the four switches are gated in the complementary mode, and these switches can obtain ZVS down to no-load with a specified peak value of im. S3 in Fig.1 is selected as an example. Fig. 3(d) shows the equivalent circuit of this procedure. The switching interval can be divided into two sub-stages. In the first sub-stage, vrect>0, and the load current can still be used to charge or discharge corresponding capacitors. As proved in Section II, when vrect=0, 50% of the final value of the voltage across C3 has been discharged. Thus, only half of the voltage across C3 needs to be charged during the secondary sub-stage. In the secondary sub-stage, vrect=0, and the energy stored in the leakage inductance is used to discharge or charge corresponding capacitors. To achieve ZVS, the following equation should be fitted:

where kT’= (kT1‧kT2) / (kT1+ kT2).

When the load current is zero, Equ. (7) can be simplified as

Fig. 5 illustrates the required Im to obtain ZVS for the primary switches down to 0 load current.

Fig. 5.Required Im to obtain ZVS down to 0 load current. (a) Vin=600V. (b) Vin=800V.

The peak-to-peak value of im is

Thus, Im is

Substituting Equ. (10) into Equ. (8) obtains

Therefore, S3 can obtain ZVS down to a zero-load current with a specific value of Lm decided by Equ. (11). Fig.6 shows the required magnetizing inductance versus Cos, Llk, and Ts. To obtain a small magnetic inductance, an air gap should be inserted in the magnetic cores. The main disadvantage caused by the added air gap is higher conduction loss of the primary coil compared with that of conventional power transformer with no air gap.

Fig. 6.Magnetizing inductance versus Cos, Llk, and Ts. (a) Ts=50 μs. (b) Llk=10 μH. (c) Cos=0.001 μF.

The conduction loss is related to the root mean square (RMS) value or average absolute value of the primary current according to different primary power devices. If metal–oxide–semiconductor field-effect transistors (MOSFETs) are used, then the conduction loss of the primary side is related only to the RMS value of the primary current. If insulated-gate bipolar transistors (IGBTs) are used, then the conduction loss of IGBTs is related to the average value of the primary current, and other conduction losses, e.g., conduction loss of the primary coil of the transformer, are related to the RMS value of the primary current. Increasing im in the proposed converter will add some conduction loss. However, the added conduction loss is much lower than that of a traditional PS controlled DC–DC converter with a larger value of im. Fig. 7 shows the magnetizing current comparison among the proposed converter and the converter in conventional PS controlled DC–DC converter. As shown in Fig. 7(a), the average value of im is zero during the half-switching period, and this current is not in phase with the load current. Thus, a larger value of im will not cause much added RMS or average absolute value of the primary current. However, as depicted in Fig. 7(b), a large value of im will significantly increase the RMS or average absolute value of the primary current and add more conduction loss in the conventional PS controlled DC–DC converter.

Fig. 7.Waveform of im: (a) the proposed converter and (b) PS controlled DC–DC converter.

Fig. 8 depicts the added conduction loss comparison caused by the increasing value of im. Im,max in Fig.6 is the peak value of im. Im,max in Fig.6 is the peak value of im, which is set as 60% of the maximum reflected output current Io,max/kT. In the proposed converter, the four primary switches are switched in the complementary mode; thus, the duty ratio of the primary side is 1. As illustrated in Fig.6, the added IGBT conduction loss in the proposed converter is only 5.8%, and other added primary side conduction loss is approximately 12%. However, the added primary conduction loss in conventional PS-controlled DC–DC converter is much higher. If D is 0.3, then the added IGBT conduction loss will be 46%, and the other added primary side conduction loss is approximately 113%. Moreover, the peak value of im in the proposed converter is increased with the input voltage, and more resonant energy can be provided to help the ZVS of the primary switches. However, in traditional PS-controlled DC–DC converter, the peak value of the magnetizing current is not varied with the input voltage. Therefore, the proposed converter is expected to have higher efficiency compared with conventional TLDCs, especially in high-input applications.

Fig. 8.Added primary side conduction loss:(a) added IGBT conduction loss and(b) other added primary conduction loss.

B. ZCS of Secondary Switches

As proved in Fig. 3, all secondary switches can obtain ZCS independent of the load condition.Sse2 is selected as an example. As shown in Fig. 3(a), Sse2 is on at this stage. However, the current of Sse2 is zero because of the reverse voltage applied to Do2. As shown in Fig. 3(b), Sse2 is switched off at zero current. Therefore, the switching loss of secondary switches can be minimized.

C. Turn Ratios and Ideal Output Characteristics

As discussed in Section II, the output is regulated by the phase angle among secondary switches and primary switches, and the turn ratios of the proposed converter should be designed according to the range of the input voltage. At maximum input voltage, the phase angle between S1 and Sse1 is zero; the primary side powers the load through Ts2. With the decrease in the input voltage, the phase angle between S1 and Sse1 is increase, and the primary side powers the load through both Ts1 and Ts2. Hence, the turn ratios of proposed converter should be designed as

and

As for a converter with 600 to 800 V input and 300 V output (used in the prototype), kT2 can be decided by Equ. (12), and the value is 1.33; according to Equ. (13), kT1=4.03.

During normal operation, the ideal relationship between the output voltage and the input voltage can be achieved by neglecting the effect of the leakage inductance, and Vo is

where D is the duty ratio of voltage level Vin/2kT’, and Equ. (14) can be further simplified as

During soft start operation, the ideal relationship between output voltage and input voltage is

where D is the duty ratio of voltage level Vin/2kT2.

D. Reduced Output Inductance Value

The reduction of the output inductance with TL secondary rectified voltage waveform has been discussed in several works [17]-[21]. According to these references, if Vinmax: Vinmin=2:1, the required output inductance of the converters with TL secondary rectified voltage waveform is approximately one-third that of conventional converters with two-level secondary rectified voltage. Therefore, the volume of the output filter in the proposed converter can be reduced significantly.

E. Comparison

The proposed converter is compared with conventional diode-clamped TLDC and a TLCDC with four primary switches in this part. The circuits of the converters for comparison are provided in Fig.9, and the detailed operation principle about these converters can be found in[1] and [21]. Table III illustrates the component number comparison among these converters, and the current and voltage rating of the primary components is provided in Table IV. Power loss comparison is listed in Table V.

Fig. 9.Converters for comparison: (a) diode-clamped TLDC in [1] and (b) TLCDC in [21].

TABLE IIICOMPONENT COMPARISON

TABLE IVCURRENT AND VOLTAGE RATING OF PRIMARY COMPONENTS (PER UNIT) (VOLTAGE: V, CURRENT: I)

TABLE VPOWER LOSS DISTRIBUTION COMPARISON (PER UNIT)

As illustrated in Table III, the proposed converter and the converter in Fig. 9(a) have the minimum number of primary components. A small number of primary devices mean not only cheaper bill-of-material cost but also a simple and compact primary structure. As proved in Table IV, two flying capacitors in Fig. 9(b) sustain higher current stress. Hence, a high capacitance is required to minimize the voltage ripple applied on these capacitors. High VA rating and capacitance corresponds to a large volume of these capacitors.

As shown in Table IV, the current stress of the primary switches in Fig. 9(b) is extremely uneven. The current stress of S3 and S2 is approximately three times greater than that of S1 and S4. The uneven current stress distribution may cause several problems, i.e., selection of appropriate switches, current sharing among parallel connected components, and complexity of drive circuit and designing of heat sink. These problems are the drawback of the converter in Fig. 9(b). During normal operation, the current stress of Dcl1 and Dcl2 in the proposed converter is zero; according to Table IV, the current stress of Dcl1 and Dcl2 in the proposed converter is also smaller during a soft start operation. Thus, the required semiconductor area of Dcl1 and Dcl2 and corresponding heat sink of the proposed converter is smallest among the three converters. Furthermore, less current stress of Dcl1 and Dcl2 means a small reverse recovery problem; thus, the main switches in the proposed converter can be kept safely in the safe operating area even during fast dynamic instant. As proved in [1] and [21], the primary current flows through clamping diodes during freewheeling stages. Thus, the clamping diodes and the main switches in Fig.9 are strongly recommended to be integrated into a power module by the producer to ensure safe operation. Although the producers of power electronics devices have provided some type-integrated diode-clamped TL power modules, the voltage and current ratings, selected range, cost, and the performance of these modules is still more unsatisfactory than that of widely used two-level HB power modules. Therefore, the proposed converter allows users to achieve high input DC–DC power conversion by easily available, cheap, and good-performance two-level power modules without sacrificing safety.

The VA rating of power transformers in Fig. 9 (a) is smaller in variable input voltage and constant output voltage applications. When the input voltage range is 2:1, the total VA rating is approximately 0.67 times that of the other two converters [19]. However, in constant input voltage and variable output voltage applications, the three circuits have the same VA rating for the transformers. The output inductance of the converter in Fig. 9 (a) is approximately three times that of other converters because the secondary rectified voltage is a two-level waveform. Furthermore, the volume of the input filter of the converter in Fig. 9 (a) is also the largest among the three converters. Thus, the overall magnetic component volume of the proposed converter and the converter in Fig.9 (b) is smaller than that of Fig. 9 (a). As shown in Table III, the proposed converter has the maximum secondary power device number. The required semiconductor area of the secondary power devices in the proposed converter is also the highest.

The power loss comparison in Table V is estimated based on the parameters used in the prototype. The input voltage is 600V, and the output is 300V/40A. As shown in Table V, the proposed converter has the smallest primary power loss caused by the minimum switching loss and no freewheeling circulating conduction loss. For the secondary side, the power loss in the proposed converter is slightly higher because of the added secondary switches. However, the added switching loss is smaller because of the ZCS operation, and the added conduction loss is also smaller because of the smaller conduction resistance of the secondary switches. Therefore, the proposed converter will have higher efficiency among the three converters, particularly under light loads, high frequency, or high input operation.

 

IV. EXPERIMENTAL RESULTS

The performance of the proposed converter is verified by a 15 kW (300 V/50 A) prototype and the input voltage is varied from 600–800 V. The main parameters of the prototype are as follows: primary switches (IGBT), 75A/600 V; secondary switches (MOSFET), 61A/250V*4; rectifier diodes, 200A/1200V; kTs1=4.03; kTs2=1.33; Lo=0.1 mH; Co=1000 μF; and switching frequency, 20 kHz. To ensure safe ZVS for the primary switches, Im is set as 60% of the maximum equivalent output current in the primary side Io,max/kT2.In the efficiency test, the converters in Fig. 9 are also tested for comparison, and these converters are designed on the same baseline.

As shown in Figs. 10(a) and 10(b), the off-state voltage of the primary switches in the proposed converter is even, and the midpoint voltage of the input capacitors is stable and equals Vin/2.As proven in 10(c), the voltage applied to the primary coil is Vin/2, and iLlk is not a constant value because im is enlarged to help the ZVS of the primary switches. The added primary RMS current is smaller because im is not in phase with the load current. Thus, the added conduction loss is also smaller. The duty ratio of Tp is 100% and uncontrolled during the whole operation stages, which means no primary freewheeling circulating conduction loss occurred. The secondary rectified voltage and iLo are provided in Figs. 10(d). As proven in Figs. 10(d), the secondary rectified voltage is a TL waveform, which can significantly reduce the volume of the output filter. The output voltage is adjusted by changing the time of Vin/2kT’ in Figs. 10(d). The ZVS characteristics of the primary switches in the proposed converter are tested with 10% load current. The waveforms of the gate signals and the collector–emitter voltages of switches S1 and S4 are depicted in Figs. 10(e) and Figs. 10(f). In Figs. 10(e), the gate–emitter voltage of S1 is much lower than the gate–emitter threshold voltage when the collector–emitter voltage of S1 decreases to zero; thus, S1 can obtain ZVS. As shown in Figs. 10(f), S4 can also obtain ZVS in a wide load range. The waveforms of the drain–source voltage and current of Sse1 are shown in Figs. 10(g). As shown in the figure, Sse1 can obtain ZCS. The primary voltage and current waveform during soft start operation is provided in Figs. 10(h).

Fig.10.Waveforms of the proposed converter: (a) vCE(S1) and vCE(S2); (b) vCE(S1) and vCE(S3); (c) vAB and ilk; (d) iLo and vrect; (d) vGE(S1) and vCE(S1); (f) vGE(S4) and vCE(S4); (g) vDS(Sse1) and iDS(Sse1); and (h) vAB and iLlk during soft start operation.

Fig. 11(a) shows the efficiency comparison under different load currents with 600 V input voltage. The proposed converter has higher efficiency because all the switches can obtain ZVS in a wide load range. The efficiency comparison under different input voltages with 40 A output is provided in Fig. 11(b), and the efficiency curves of all the converters decrease the increase in input voltage. The decreasing slope of the proposed converter is smaller than that of others because the magnetizing inductance can provide more resonant energy. Thus, the proposed converter is more suitable for high-input applications.

Fig. 11.Efficiency comparison: (a) variable output current, Vin=600V; and (b) variable input voltage, Io=40A.

 

V. CONCLUSION

A new four-primary-switch diode-clamped soft switching TLDC with full ZVS load range and TL secondary voltage waveform has been proposed. The operation principle and characteristics of the presented converter are discussed, and the experimental results are consistent with theoretical predictions. The improvements of the proposed converter include a simple and compact primary structure, TL secondary rectified voltage waveform, wide load range ZVS for all primary switches, and full output regulated range with soft switching operation. The proposed converter also has some disadvantages. The VA rating of the transformer is slightly larger than that of conventional TLDCs in variable input and constant output mode. The conduction loss of the primary coil is slightly higher because an air gap is inserted into the magnetic cores of the transformer. Finally, the secondary circuit is slightly complex.