I. INTRODUCTION

The zero-voltage-switching (ZVS) phase-shifted full-bridge (PSFB) converter is the most popular topology in the power range of a few kilowatts (1-5kW) for battery chargers [1]-[3]. Its most attractive features include constant switching frequency operation, high power density, and ZVS turn-on of the primary switches [4]-[9].

Dead-time is a key parameter in the PSFB converter, for both ZVS operation and for system performance. It is well known that the ZVS of PSFB converters is achieved by utilizing the energy stored in the resonant inductance to charge the parasitic capacitors of MOSFETs during the dead-time interval [10], [11]. Meanwhile, the switches are supposed to be turned on before the commutation of the primary current. Thus, there is a minimum and a maximum limitation of the dead-time for ZVS [12]. In addition, a long dead-time may be more reliable. However, along dead-time will make the adjustment range of the duty cycle narrow and reduces the dynamic performance of the converter [13]. Therefore, ZVS cannot be achieved over a wide load range or system performance will be degraded if the dead-time is incorrectly selected.

A lot of research has focused on studying the dead-time for ZVS. In [12]-[14], an adaptive dead-time control scheme for high frequency dual active bridge converters is given. The main influencing factors of dead-time are studied. In [15] and [16], the relationship between resonant inductance and dead-time is analyzed. Equations for calculating the resonant inductance required to achieve ZVS are presented while incorporating the effect of magnetizing current and dead-time. All of these studies are conducive to setting the dead-time and can improve the performances of the PSFB converter to a certain extent.

However, research on the dead-time for ZVS in PSFB is seldom studied comprehensively, especially for battery charger applications with a wide output power range. To be specific, the assumption that the output filter inductance remains constant is no longer valid over a wide load range. Actually, the inductance varies a lot with load changes and the primary current is affected significantly. In addition, the Miller Plateau was rarely considered in previous works, even though it occupies a part of dead-time. More importantly, the length of the Miller Plateau also varies with the output current. Furthermore, a blocking capacitor, which is introduced to prevent the transformer from becoming saturated, would considerably reduce the circulating current and consequentially affect the dead-time. In order to achieve ZVS over a wide power range, the factors mentioned above must be well considered.

Building on the aforementioned works, this paper presents a comprehensive analysis and calculation of the dead-time for ZVS over a wide load range, taking into consideration the effects of the Miller plateau, the nonlinear characteristic of the output filter inductance and the blocking capacitor. This paper is organized as follows. Section II introduces a traditional analysis of dead-time and typical experimental phenomena caused by the above mentioned effects. A comprehensive theoretical analysis and analytical equations of the dead-time are proposed in Section III. In Section IV, detailed experimental results are given to verify the theoretical analysis.

 

II. DEAD-TIME FOR ZVS IN THE PSFB TOPOLOGY

A basic circuit diagram of a PSFB converter is shown in Fig. 1(a). It is formed by four switches Q1-Q4, a power transformer Tr, a resonant inductor LR(including the leakage inductor), output rectifier diodes DR1 and DR2, the output filter inductor Lf and the capacitor Cf. Q1 and Q2 are switched on/off before Q3 and Q4. Thus, Q1 and Q2 are known as the “leading leg”, while Q3 and Q4 are known as the “lagging leg”. The two switches of each leg are driven by complementary PWM signals with a dead-time inserted between them. Vin is the input voltage. Vpri is the voltage across the primary winding of the transformer Tr, and Ip is the current through it. The battery voltage is Vo. Since it is easy to achieve ZVS of the leading leg, the dead-time for ZVS of the lagging leg is mainly discussed here.

Fig. 1.(a) PSFB converter topology. (b) Key waveforms of the PSFB converter.

A. Traditional Analysis and Calculation of Dead-Time

Key waveforms of a PSFB converter are shown in Fig. 1(b). Take the ZVS-on of Q3as an example. Q4 is switched off at t4. Then the ZVS of Q3is achieved by utilizing the energy stored in the resonant inductance LR to charge the parasitic capacitors of the MOSFETs (Cds3 and Cds4) during the time period t4-t5. Since Vpri is equal to zero, an equivalent circuit during this transition interval is shown in Fig. 2. Therefore, based on Fig. 2, the following equations can be obtained

Where Vds4(t) is the voltage across Cds4, and IP(t) is the primary current. Cds3 = Cds4= Cds. Then, during t4-t5,Vds4(t) and Ip(t) can be deduced as [17]:

Where IP(t4) is the primary current at t4, and:

Fig. 2.Equivalent circuit during t4-t5.

Vds4(t) can reach Vin at the end of the transition interval. Thus, based on (3), the minimum time tr required for this transition can be deduced as:

The minimum dead-time consists of the turn-off delay time of the MOSFET td-off and the transition interval [12]. This can be expressed as:

Meanwhile, if the dead-time is too long, the switch Q3 turns on after the primary current IPcommutation. The ZVS of Q3fails since the voltage across the drain-to-source is increasing. After the voltage transition, Vin is impressed across the resonant inductance. Therefore, the primary current ramps down from t5.

Ip reaches zero at t6. The time interval t56 can be deduced as:

Therefore, the maximum dead-time can be given as:

The primary current at t4 and t5can be derived as follows. At t0, the primary current is equal to the reflected output current [18].

Where Io is the output current, ΔIo/2 is the output current ripple, and N is the turn ratio of the transformer. ΔIo can be expressed as:

Where Lf is the value of the output filter inductance, Vo is the output voltage, Ts is the switching cycle, and Deff is the effective duty cycle.

During the time period t0-t1, the input voltage Vin is mainly impressed across the magnetizing inductance. The magnetizing current increases linearly in this time period. From (10), (11) and (12), the primary current at time t1 can be calculated as:

Where ILm is the magnetizing current, and Lm is the magnetizing inductance of the transformer.

During the time period t1-t3, Q1 is turned off, the charging of Cds1 and Cds2 is practically conducted by constant current, and the energy is provided by the output inductor Lf with its current reflected to the primary side. Similar to the calculation process presented in (1)-(4), the primary current at t3 can be expressed as:

During t3-t4, the primary current, which is thought to be constant, is freewheeling through the primary side.

During the time period t4-t5, Q4 is turned off. The primary current begins to charge the parasitic capacitors of Q4 and Q3, and Cds4 and Cds3. Then the primary current at t5 can be deduced using (4) and (5).

Detailed formulas for the minimum dead-time and the maximum dead-time can be deduced by substituting (10)-(16) into (6) and (9).

However, the traditional analysis is not comprehensive since many factors are not considered.

B. Nonlinear Output Filter Inductance Phenomenon

The output filter inductance is thought to be constant in the traditional analysis. However, when the nonlinear magnetizing permeability of the core material is considered, the actual value of the output filter inductance is variable over a wide load range. Fig. 3 gives experimental waveforms of the current through the output filter inductor in a PSFB converter under different loads (with the same input and output voltages). In Fig. 3, the output filter inductance with a 15A load decreases drastically compared to the 7A load condition. According to (13), the output filter inductance has a significant effect on the primary current. The calculation of the dead-time is affected correspondingly.

Fig. 3.Experimental waveforms of the output filter inductance current. (a) Io=7A. (b) Io=15A.

C. Miller Plateau Phenomenon

As a part of the dead-time, the length of the Miller Plateau varies with the load current. Fig. 4 gives experimental waveforms of the switching signals of Q4.

Fig. 4.The experimental switching waveforms of Q4. (a) Io=3A. (b) Io=15A.

From Fig. 4, there is a Miller Plateau during the turn-off procedure of Q4. An obvious difference inthe length of the Miller Plateau between the two kinds of operating conditions is observed. The length of the Miller Plateau at a 3A load is much shorter than that at a 15A load. Therefore, the affection of the Miller Plateau is significant when the converter operates over a wide load range and should be taken into consideration.

D. Blocking Capacitor Effect

Ideally, the magnetizing current has no dc bias since the PSFB converter has a symmetrical structure. However, the offset on the magnetizing current appears in practice despite this symmetry. A simple way to prevent the transformer from becoming saturated is to introduce a blocking capacitor in series with the primary winding, as shown in Fig. 5(a). However, the performance of the PSFB converter and the calculation of the dead-time will be affected significantly when the blocking capacitor is considered. Fig. 5(b) and (c) give the waveforms of the primary current without and with the blocking capacitor. From Fig. 5, obvious differences in the primary current can be observed. Consequentially, the setting of the dead-time is affected consequentially.

Fig. 5.(a) PSFB converter with blocking capacitor. (b) Primary current without blocking capacitor. (c) Primary current with blocking capacitor.

Based on the descriptions above, phenomena such as the nonlinear output filter inductance, the Miller Plateau and the blocking capacitor effect are important for accurately calculating the dead-time in PSFB converters over a wide load range. The detailed analysis and equation derivations will be presented in the next section.

 

III. COMPREHENSIVE ANALYSIS AND CALCULATION OF DEAD-TIME

A. Effect of the Nonlinear Output Filter Inductance

It is well known that permeability is nonlinear when the current flowing through the inductance varies [19]. With an increase incurrent, the energy stored in the inductance increases and the permeability becomes closer to saturation. Normally, when considering the restrictions of size and cost, the output inductor is designed at the full-load operating condition with an allowable maximum stored magnetizing capability before actual magnetizing saturation. Therefore, the nonlinear characteristic of the inductance is certain to exist when it operates over a wide load range according to the magnetization curve.

Fig. 6 gives a fitting curve of the output filter inductance with respect to different load currents. Based on the analysis in [19], the relationship between the current and the nonlinear inductance can be modeled by an m’s order polynomial equation as:

Where αk and m are constants that can be obtained from the magnetizing core datasheet by the curve fitting method.

Fig. 6.Nonlinear characteristic of the output filter inductance.

Based on (13) and (17), the primary current at t1 can be rewritten as:

Therefore, according to (18), the nonlinear characteristic of Lf influences the primary current at t1. The slope of the primary current has a similar variation as the output current ripple. Thus, calculation of the dead-time is inevitably affected.

In conclusion, the output current ripple changes with the load current because of the nonlinearity of the output filter inductance. When it is reflected to the primary side, the slope of the primary current has a similar variation. With a larger load current, the output current ripple and the slope of the primary current also become larger.

B. Effect of the Miller Plateau

The turn-on/off procedure of the MOSFET is a part of the dead-time. Since the switches in the PSFB converter can achieve ZVS-on, there is no Miller Plateau in the turn-on procedure. However, a Miller Plateau occurs during the turn-off procedure because the parasitic capacitors Cds of the two switches are charged in this interval. Moreover, the load current has a significant affection on the length of the Miller Plateau. Detail analyses are shown as follows.

The turn-off procedure of the switch Q4 is shown in Fig. 7 (a). The time period t4-t5 is divided into three intervals. Therefore, the minimum dead-time of the PSFB converter can be expressed as:

Fig. 7.(a) Turn-off procedure of MOSFET. (b) Nonlinear characteristic of the parasitic capacitance of the MOSFET with respect to the drain-to-source voltage Vds.

Interval 1[t4-ta]: It is the overdrive section, where it is necessary to discharge the gate-to-source capacitor Cgs and the gate-to-drain capacitor Cgd from the overdrive voltage to the Miller plateau level.

Where Idri and Vdri are the driving current and voltage. Vgspl is the gate-to-source voltage at the beginning of the Miller Plateau.

Interval 2[ta-tb]: This is the Miller Plateau. This stage begins the moment the gate-to-source voltage Vgs decreases to the Miller Plateau level Vgspl. During this stage, the gate-to-drain capacitor Cgd is charged by the driving current, and the drain-to-source capacitor Cds is charged by the primary current. The charging formulas of Cgd and Cds are defined as:

When the charging rate of Cgd is slower than that of Cds, the driving current is fully applied to charge Cgd. Thus, Vgs is approximately constant and the Miller Plateau occurs.

Meanwhile, the drain-to-source voltage Vds has a remarkable influence over Cgd. Fig. 7(b) shows the characteristic of Cgd with respect to Vds[20]. Cgd decreases sharply with arise of the drain-to-source voltage Vds. According to [21], Cgd is a function of Vds, and is approximated by the following equation.

where Cgd,0 and K are related factors that can be found in the datasheet of the MOSFET.

With a rising Vds, Cgd drops to a certain degree, where the charging rates of both Cgd and Cds are identical and the Miller Plateau comes to an end.

By combining (21) and (22), the gate-to-drain capacitance at the end of the Miller plateau Cgdpl can be calculated from (24).

According to (24), a larger output current means a smaller Cgdp1. In addition, according to (23), a smaller Cgdp1 means a larger Vdspl, which is the drain-to-source voltage at the end of the Miller Plateau. Therefore, the value of Vdspl increases with an increase of the output current.

Then, the drain-to-source voltage at the end of the Miller Plateau Vdspl can be derived from (23). Thus, the length of the Miller Plateau can be obtained from (21), (23) and (24).

where is the average value of Cgd in the Miller Plateau.

Interval 3[tb-t5]: This is the drain voltage transition interval when Vds rises from Vdspl to the supply the voltage Vin.

In conclusion, due to the nonlinear characteristic of the parasitic capacitance of the MOSFET, the drain-to-source voltage at the end of the Miller Plateau Vdspl increases with the load current. As a result, the length of the Miller Plateau increases since the driving current Idri is constant.

C. Effect of the Blocking Capacitor

When a blocking capacitor is introduced into the primary side of the PSFB converter in series with the transformer, ZVS of the lagging leg would be affected. The operation of the PSFB converter, especially the primary current, has distinct changes in the intervals as follows.

[t3-t4]: In this interval, the switches Q2 and Q4 are conducting and the voltage across the primary side of the transformer is clamped to zero. Due to the introduction of the blocking capacitor, a reverse voltage is impressed across the resonant inductance. Therefore, the primary current decreases in this period. The blocking capacitor and the resonant inductance form a resonant tank in this interval.

Where VCb(t) is the voltage across the blocking capacitor Cb, and Ip(t) is the primary current.

Equations (27) and (28) can be rearranged as:

The characteristic equations of (29) and (30) dictate the characteristics of IP(t) and VCb(t). The roots of the characteristic equations are:

where:

Then, IP(t) and VCb(t) can be obtained as:

where the constants A1 and B1 can be deduced based on the initial conditions IP(t3) and VCb(t3).

Using (27) and (35), A2 and B2can be obtained as:

Therefore, (32) and (33) can be rewritten as:

In order to calculated the primary current IP(t), the voltage across the blocking capacitor at t3 needs to be evaluated first. During t0-t3, the blocking capacitor is charged by the primary current. Therefore, the voltage VCb(t3) can be deduced as:

Based on the expressions of the primary current Ip in different time intervals (10), (13) and (14), the integration of the primary current can be expressed as:

According to the analysis in [22] and [23], the voltage across the blocking capacitor VCb(t) at t0 and t4havethe same value but opposite in direction.

By substituting (39) and (41) into (40), VCb(t3) can be expressed as:

where:

Dloss is the duty cycle loss and can be obtained from [17]:

The full expression of VCb(t3) can be obtained by substituting (41), (44) and (45) into (43). However, this is too long and not fully visualized here.

Therefore, the primary current at time t4 can be deduced by substituting (42) into (38).

[t4-t5]: The switch Q4 is turned off at t4. The parasitic capacitors of the switches Q3 and Q4, Cds3 and Cds4, and the resonant inductance LR form the resonant tank. The blocking capacitor does not take part in the resonant process in this time period because it is much larger than Cds3 and Cds4.

[t5-t6]: During the time period t5-t6, the switch Q2 remains on and the parasitic diode D3 is forward biased. The primary current flows through Q2 and D3. The drain voltage of the switch Q4 is clamped to one forward diode drop above the input voltage Vin. Here, a resonant tank is formed by the resonant inductance and the blocking capacitance. Thus:

Then, the primary current and the voltage across the blocking capacitor during this time period can be expressed as:

At time t6, the primary current drops to zero.

This time interval can be given as:

According to the above discussions, the primary current during the freewheeling period decreases a lot due to the ac voltage of the blocking capacitor. The ac voltage and the variation of the primary current become larger with a smaller capacitance.

D. Equations of the Dead-time

In summary, accurate formulas of the minimum and maximum dead-time, considering the effects of the nonlinear output filter inductance, the Miller Plateau and the blocking capacitor, can be concluded as follows:

whereVgsp1, Vdsp1, Ip(t4), Ip(t5) and VCb(t5) can be obtained from (24)-(25) and (46)-(48).

The theoretical analysis and calculations will be verified separately in next section.

 

IV. MEASUREMENT RESULTS

In order to verify the above analysis and calculations, a 1.5kW PSFB battery charger prototype is built. A STM32F051MCU is chosen to provide the PWM driving signals. The main parameters of the prototype are listed in Table I. Several tests are carried out separately in order to verify the above analysis.

TABLE IMAIN PARAMETERS OF THE PSFB PROTOTYPE

A. Nonlinear Output Filter Inductance Phenomenon Experiment

Fig. 8 gives experimental waveforms of the output filter inductor current and primary current with respect to different load currents.

Fig. 8.Experimental waveforms of output filter inductance current ILf and primary current Ip with respect to different load currents. (a) Io=7A. (b) Io=11A. (c) Io=15A.

The input voltage is 280V and the output voltage is controlled at 90V. From Fig. 8, it can be seen that the slope of the output filter inductance current ripple at a heavy load is larger than that at a light load. A similar difference can be observed on the slope of the primary current during the time period t0-t1, which is equal to the sum of the magnetizing current and the reflected output current ripple. It should be pointed out that there is an oscillation at t0 due to the parasitic capacitance of the output diode. In order to acquire precise results, the oscillation interval has been neglected. Therefore, the time interval may be different for each calculation. However, it has little influence on the final results. The experimental results in Fig. 8 are consistent with the analysis in Section III (A).

B. Miller Plateau Phenomenon Experiment

Fig. 9 shows the experimental results of the turn-off procedure of the MOSFET switch at different load currents. The length of the Miller Plateau and the value of Vdspl at various load currents are shown. It can be seen that the length of the Miller Plateau at a full load is much longer than that at a light load. There is also a significant difference in the voltage across drain-to-source Vdspl when the Miller Plateau ends with different load currents.

Fig. 9.Experimental waveforms of the turn-off procedure of the MOSFET. (a) Io=3A. (b) Io=7A. (c) Io=11A. (d) Io=15A.

Both the calculated and experimental results of the length of the Miller Plateau for various load currents are presented in Fig. 10. It can be seen that the two curves are almost the same. According to the experimental results, the analysis in Section III(B) is well verified.

Fig. 10.Effect of load variation on the Miller Plateau length.

C. Blocking Capacitance Effect Experiment

Fig. 11 shows experimental waveforms of the primary current with different blocking capacitances. The load current is set at 10A. From Fig. 11, it can be seen that the primary current has an obvious change during the time period t3-t4,and that the primary current changes drastically with a small blocking capacitance.

Fig. 11.Experimental waveforms of the primary current with respect to different blocking capacitances. (a) Cb=0.66μF. (b) Cb=1μF. (c) Cb=1.22μF. (d) Cb=1.66μF.

Fig. 12 gives the calculated and experimental results of the primary current variation during the time period t3-t4 for varying blocking capacitances. The two results are similar and have the same trend.

Fig. 12.Effect of the blocking capacitance variation on the primary current.

D. ZVS Experiments Compared with the Previous Method

As mentioned before, a long dead-time will make the adjustment range of the duty cycle narrow and reduce the dynamic performance of the converter. Thus, under most circumstances (especially in high frequency converters), the dead-time should be selected based on the minimum requirements. In the proposed 1.5kW PSFB battery charger prototype, the minimum dead-time which can ensure the ZVS of the MOSFETs over the load range (5~15A) is 633ns using the proposed method, and it is 595ns using the traditional analysis. A security margin of5% is added in real applications. As a result, the dead-time is selected to be 633(1+5%)=664ns and 595(1+5%)=624ns,respectively. ZVS and efficiency tests are run over a wide load range and the results are shown in Fig. 13 and Fig. 14.

Fig. 13.ZVS conditions at different loads with the minimum dead-time calculated using the conventional and the proposed method. (a) Dead-time. (b) Io=5A. (c) Io=10A. (d) Io=15A.

Fig. 14.Efficiency with the minimum dead-time.

According to Fig. 13, the ZVS of Q4 in the lagging leg is achieved from a full load to the minimum load when the dead-time is selected to be 660ns using the proposed method. Meanwhile, the ZVS of the lagging leg failed when the load current was smaller than 10A with 620ns calculated by the conventional analysis.

The tiny difference between the selected value and real-time applications is due to the limitation of the digital PWM resolution. The efficiency curve in Fig. 14 verifies the ZVS results. While the efficiency with the proposed method is maintained when the output current is higher than 10 A, it shows a higher level under light load conditions compared to the conventional method.

In addition, in some low frequency applications, the dead-time has a weak influence on the adjustment range of the duty cycle. A long dead-time is preferred by designers to avoid shoot-through problems. Similarly, the dead-time is set to 997 (1-5%)=947ns based on the proposed method and 1597(1-5%)=1517ns based on the conventional analysis. ZVS and efficiency tests are run over a wide load range and the results are shown in Fig. 15 and Fig. 16.

Fig. 15.ZVS conditions at different loads with the maximum dead-time calculated using the conventional and the proposed method. (a) Dead-time. (b) Io=5A. (c) Io=10A. (d) Io=15A.

Fig. 16.Efficiency with the maximum dead-time.

According to Fig. 15, the ZVS of Q4 in the lagging leg is achieved from a full load to the minimum load when the dead-time is selected to be 940ns using the proposed method, while the ZVS of the lagging leg failed with a 1520ns dead-time calculated by the conventional analysis. The improved efficiency is shown in Fig. 16.

Furthermore, experimental results of the dead-time range for ZVS and the calculation results using the proposed method when the input voltage or load current changes are shown in Fig. 17. In Fig. 17(a), when the input voltage is fixed at 310Vdc, the dead-time range obtained from the proposed method and the experimental results are given with load changes from 5A to 15A.In addition, when the output terminal is fixed at 7A and 70V, the dead-time ranges obtained from the proposed method and the experimental results are given with input voltage changes from 200Vdc to 380Vdc, as shown in Fig. 17(b). The experimental results of the dead-time range are obtained from massive ZVS tests, and dead-time changes with a 10ns step, which is the minimum resolution of the digital PWM in the proposed prototype. According to Fig. 17, the dead-time calculated using the proposed method matches well with the experimental results.

Fig. 17.Calculated and experimental results of the dead-time range. (a) The load varies from 5A to 15A. (b) The input voltage varies from200Vdc to 380Vdc.

Therefore, using the proposed method, an optimal dead-time can be selected to meet the specific requirements of a system. At the same time, ZVS can be achieved over a wide load range. Strictly speaking, when ZVS failed with the dead-time calculated using the conventional method, system designers can adjust the dead-time and run the ZVS tests again until ZVS is achieved. However, it is time consuming, and more importantly, the optimal dead-time is very hard to determine by experiments.

 

V. CONCLUSIONS

Dead-time for the ZVS in a battery charger with the PSFB topology is comprehensively analyzed and calculated in this paper. The effects of the nonlinear output filter inductance, the Miller Plateau length and the blocking capacitor are considered and analyzed for the first time. Based on these, analytical equations of the dead-time range for ZVS are deduced. A 1.5kW prototype is built to verify the above analysis. The analysis results of the three effects are verified separately. Subsequently, ZVS experimental results show that, compared to traditional analysis, the optimal dead-time can be obtained from the proposed method to meet specific system requirements and to achieve ZVS over the entire load range at the same time.