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An Excess Carrier Lifetime Extraction Method for Physics-based IGBT Models

  • Fu, Guicui (School of Reliability and System Engineering, Beihang University) ;
  • Xue, Peng (School of Reliability and System Engineering, Beihang University)
  • Received : 2015.06.21
  • Accepted : 2015.11.11
  • Published : 2016.03.20

Abstract

An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

Keywords

I. INTRODUCTION

In recent years, the characterization and modeling of insulated gate bipolar transistors (IGBTs) have been greatly improved [1]–[6]. In particular, the physics-based models for non-punch-through (NPT), punch-through (PT), and field-stop (FS) IGBTs have become increasingly accurate. However, precise IGBT models are not enough. Thus, including a parameter extraction method that can accurately extract the parameters needed for the models is necessary.

Excess carrier lifetime is one of the most important parameters for physics-based IGBT models, which characterize the tail current during the turn-off transient and on-state voltage drop. Although many works have explored lifetime extraction [7]-[19], most of them use the extraction theory cited in [7] to extract excess carrier lifetime for NPT IGBT models, as well as the extraction theory cited in [17] to extract excess carrier lifetime for PT or FS IGBT models. Since the significant development of IGBT transient modeling theory, especially the availability of the newly proposed expression for the transient dynamics of excess carrier distribution in the N-base [4] and the improved understanding of the transient modeling of FS layers [5], extraction methods should be modified to meet the latest developments. Moreover, many existing studies validated their extraction methods by comparing the experimental and simulated characteristics of IGBTs at static and transient states. Such validation approach is not enough. As simulation accuracy depends on many factors, the accuracy of simulation results cannot guarantee the accuracy of extraction methods.

In the present study, an excess carrier lifetime extraction method for physics-based IGBT models is is proposed on the basis of the latest development in IGBT modeling theory [4], [5]. The Sentaurus simulation is used to validate the proposed method. In the validation, the Sentaurus 2D mixed-mode simulation is used to simulate the clamp voltage turn-off test. The proposed extraction method is implemented with the simulation data. Finally, the comparison between the extracted results and the actual lifetime obtained from the numerical device model validates the proposed method.

 

II. EXCESS CARRIER LIFETIME EXTRACTION METHOD

The excess carrier lifetime is extracted by the tail current at a constant voltage supply, which is obtained from the clamp voltage turn-off test. For NPT IGBTs, the extraction of N-base lifetime τL is independent of clamp voltage. For PT and FS IGBTs, a low clamp voltage extraction is needed to acquire the N-base lifetime τL , and a high clamp voltage extraction is necessary to obtain the buffer layer lifetime τH .

A. Extraction of τL for NPT IGBT Models

According to Hefner’s IGBT modeling theory [7], during the turn-off transient state, the base charge decay rate is

where QL is the excess carrier charge in the N-base, τL is the excess carrier lifetime in the N-base, and In0 is the electron current injected into the emitter.

QL in (1) is expressed as [7]

where WL is the undepleted N-base width. DP is the hole diffusivity in the N-base, and IT is the total current.

In0 (1) is expressed as [7]

where ni is the intrinsic carrier concentration, Isne is the emitter electron saturation current, and P0 is the excess carrier concentration at the emitter edge of the N-base.

At the turn-off transient state, if the anode voltage rise time is prolonged, then few electrons can arrive to the P emitter to provide the electrons needed for recombination. The local electrons and holes thereby have to recombine, which results in the decrement of P0 . As In0 is proportional to the square of P0 , In0 dramatically drops when P0 decreases. Therefore, in prolonging the anode voltage rise time, In0 in (1) can be neglected. Substituting (2) into (1) yields

The current decay rate (-[dlnIT/dt]-1) decreases at a low current because the N-base leaves a high-level injection condition and the low-level lifetime is shorter than the high-level lifetime. At a high current, the current decay rate also decreases because the increased rate of emitter electron current injection [7]. In the range in which the current decay rate is at its maximum, the N-base is in a high-level injection state, and the electron current injection is negligible, (4) is valid. τL is equal to the maximum value of the current decay rate.

B. Extraction of τL and τH for PT IGBT Models

In a PT IGBT, the N-base is in a high-level injection condition. Therefore, the whole current transmission equation takes the form of the following bipolar transport equation [20]:

where DL = 2DNLDPL / (DNL + DPL). DNL and DPL are the electron and hole diffusivities in the N-base, respectively. bL = μNL / μPL. μNL and μPL are the electron and hole mobilities in the N-base, respectively. δp is the excess hole concentration, and A is the device active area.

At the turn-off transient state, the N-base excess hole distribution is [4], [5]

where WL is the width of the undepleted N-base, PL0 is the excess carrier concentration at x = 0 (Fig. 1), and LL is the base diffusion length

Fig. 1.Coordinate diagram for the PT and FS IGBTs.

In the clamp voltage turn-off test, after the anode voltage reaches the clamp voltage, the anode voltage remains constant. Therefore, dWL / dt in (6) is zero. By combining (5) and (6) while neglecting the second term of (6), we can obtain the base hole currents Ip1 and Ip2 in Fig. 1.

where τAb is the ambipolar base transit time The N-base excess charge is QL = qPL0WL / 2.

In the PT buffer layer, the low-level injection is assumed, and the hole current IpH is [20]

where WH is the buffer layer width. NH is the buffer layer doping concentration. PH0 and PHW are the excess carrier concentrations at x* = 0 and x* = WH , respectively. QH is the excess charge in the buffer layer, that is, QH = qAWH (PH0 + PHW) / 2. QB is the base charge, that is, QB = qAWLNL. τHb is the buffer layer base transit time, that is,

Note that NL << NH and that the second term on the right side of (9) is much smaller than the first term [5]. By equating (7) and (9) while neglecting the second term of (9), we can express the base charge QL as

where QT is the total excess charge in the N-base and buffer layer. QT = QH + QL. By substituting (10) into (8), the hole current Ip2 at x = WL, which is now the total current, is given by

The total charge decay rate is [20]

where τH is the excess carrier lifetime in a high-doped buffer layer.

For the high clamp voltage extraction WL ≈ 0 , (11) is simplified as

Substituting (13) into (12) with WL = 0 yields (14).

The first term on the right side of (14) corresponds to the excess charge recombination in the buffer layer, whereas the second term denotes the emitter electron current injection. The excess charge recombination rate in the buffer layer is much larger than the electron injection rate because τH is very short. If the second term on the right side of (14) can be neglected, then (15) is obtained.

At a high current, the buffer layer leaves the low-level injection condition. The current decay rate thereby increases because the high-level lifetime is longer than the low-level lifetime. At a low current, the excess charge in the buffer layer is almost exhausted, and the current decay is dominated by the electron current injection. The current decay rate increases because of the decreased rate of emitter electron current injection. In the minimum current range, in which the buffer layer is in a low-level injection condition and the electron current injection is negligible, (15) is valid. τH is equal to the minimum value of the current decay rate.

For the low clamp voltage extraction, τAb << τL is observed, and (11) is simplified as

The anode voltage rise time is prolonged. Few electrons can reach the J0 junction to provide the electrons needed for recombination. Therefore, the local electrons and holes are recombined, and PH0 is decreased. The excess carrier recombination rate is very large because the excess carrier lifetime in the buffer layer is very short. Thus, PH0 greatly decreases as a result of the recombination. In the PT IGBT, the electron current injected into the emitter is [17]

The electron current InH injected into the emitter is thereby negligible because of the significant decrement of PH0 .

The anode voltage rise time is prolonged to eliminate electron current injection. The terms containing Isne in (12) correspond to the electron current injection. By neglecting the terms containing Isne in (12), substituting (16) into (12) yields

where

and

According to the discussion on (4), (18) is only validated in the range in which the current decay rate is at its maximum. In this range, IT is much smaller than Therefore, is approximately equal to the maximum current decay rate, which can be used in (19) to calculate τL .

C. Extraction of τL and τH for FS IGBT Models

In the FS IGBT, the N-base is also in a high-level injection condition; hence, equations (5)–(8) are still valid. However, unlike the PT buffer layer, the FS layer is in a high-level injection condition [5]; therefore, (9) should be modified as

The doping concentration in the FS layer is about 1×1015cm-3 -1×1016cm-3 ; thus, bH ≈ bL . As NL << NH , the third term of (21) can be neglected [5]. By equating (7) and (21), the base charge QL is expressed as

By substituting (22) into (8), the collector current, which is now the total current, is given by

For the high clamp voltage extraction, (23) is simplified as follows because WL ≈ 0 :

According to the discussion in (14), the emitter electron current injection is negligible. By eliminating the terms containing Isne in (12), substituting (24) into (12) with WL = 0 yields

The current decay rate decreases at a high current because of the increased rate of electron injection into the emitter. At a low current, the current decay rate also decreases because the FS layer leaves a high-level injection condition. Therefore, in the maximum current range, in which the FS layer is in a high-level injection condition and the electron current injection is negligible, (25) is valid. The maximum current decay rate can be used in (25) to calculate τH .

For the low clamp voltage extraction, τAb << τL ; hence, (23) is simplified as

where

and

According to the discussion on (4), (27) is also valid in the range in which the current decay rate is at its maximum. In this range, IT is much smaller than Therefore, is equal to the maximum current decay rate, which can be used in (28) to calculate τL .

 

III. NUMERICAL SIMULATION

To validate the proposed extraction method, the tail current is obtained with the 2D Sentaurus numerical simulation. In the simulation, the test circuits (Fig. 2) are used to simulate the clamp voltage turn-off test. Through the Sentaurus mixed-mode simulation, all the diodes, resistors, and inductors used in the test are implemented with built-in Sentaurus compact models. The NPT, PT, and FS IGBTs under testing are implemented with 2D numerical device models. Table 2 shows the parameters used in the 2D numerical device models.

Fig. 2.Test circuit used for excess lifetime extraction. (a) Circuit used to extract τL for NPT IGBT and τH for FS or PT IGBT. (b) Circuit used to extract τL for the FS or PT IGBT.

According to the mixed-mode simulation, the turn-off waveforms of the clamp voltage can be obtained. The typical and simulated turn-off waveforms are shown in Figs. 3 and 4, respectively. Fig. 3 shows that the turn-off transient condition of the IGBT can be divided into four phases. In phase 1, the gate-side capacitance discharges, and the gate voltage Vg decreases accordingly. In phase 2, as a result of the Miller effect, Vg remains approximately constant. Vce starts to rise slowly while the collector current Ic remains unchanged. As the collector-emitter voltage Vce increases to approximately 10 V, phase 3 begins. Vce begins to increase rapidly toward Vdc. In this phase, the collector-emitter depletion capacitance begins to charge. The charging current greatly compensates for the collector current reduction because of the shrinking of the MOS-side electron current. The collector current Ic then undergoes a slow decrease. Once Vce reaches the Vclamp, phase 4 begins. The diode begins to conduct, and the collector current of the IGBT starts to transfer into the diode. Given that Vge is under the threshold voltage Vth, the MOS-side electron current and the associated hole drift current are removed. This effect results in an initial rapid decline of the collector current Ic. The collector current Ic then continues to decline because of the remaining excess carrier recombination in the N-base and buffer layer.

Fig. 3.Typical waveforms of IGBT turn-off process.

Fig. 4.Turn-off waveforms of the simulated clamp voltage of the NPT IGBT using Rg = 5kΩ at 150 V/50 A.

TABLE I2D NUMERICAL DEVICE MODEL PARAMETER LIST

As shown in Fig. 3, the duration of phase 3 and that of phase 4 are defined as tr and tL, respectively. During tL, the excess carrier in the N-base and buffer layer undergo slow recombination. The current decay rate during tL can thus be used to extract the excess carrier lifetime. tr is the anode voltage rise time. To eliminate the excess carrier concentration P0 at the emitter edge of the N-base, tr should be long enough. In the range in which the extracted carrier lifetime is independent of tr, the extracted results are equal to the real carrier lifetime.

 

IV. EXTRACTION METHOD VALIDATION

On the basis of the simulated tail current, the proposed lifetime extraction method is performed to extract the excess carrier lifetime. The extraction method is directly validated by comparing its excess carrier lifetime with the actual excess carrier lifetime obtained from the 2D numerical device model.

A. Excess lifetime extraction for NPT IGBT models

The circuit in Fig. 2a is used to simulate the turn-off test. In the circuit, the clamp voltage Vclamp is 150 V, the inductor L is 2 mH, the source voltage Vcc is 500 V, the capacitance C1 is 50 mF, the load resistor R1 is 5 Ω , and the gate resistor Rg1 is varied to change the anode voltage rise time.

The turn-off tests are simulated with six different anode voltage rise times at 150 V/50 A. On the basis of the simulated tail current, the current decay rate is calculated with (4), as shown in Fig. 5. In the range in which the maximum current decay rate is independent of the anode voltage rise time, τL is extracted to be 6.01 μs . The actual lifetime τL obtained from the NPT IGBT device model is 6.2 μs , which is very close to the extracted value.

Fig. 5.Current decay rate versus total current for NPT IGBT.

B. Excess Lifetime Extraction for PT IGBT Models

For the high clamp voltage extraction of the PT IGBT, the test circuit in Fig. 2a is used to extract τH . In the circuit, the inductor L is 2 mH, the gate resistor Rg1 is set to zero, the voltage of Vcc is 600 V, the capacitance C1 is 50 mF, the load resistor R1 is 5 Ω , and the clamp voltage Vclamp ranges from 300 V to 550 V. This extraction is performed to verify that the proposed method can provide a reasonable extraction result at different clamp voltages.

The turn-off test is simulated at 50 A. The current decay rate is then calculated with (15). τH is extracted by finding the minimum value of the current decay rate. Fig. 6 shows the extracted τH at different clamp voltages.

Fig. 6.Extracted τH versus clamp voltage for PT IGBT.

For the low clamp voltage extraction, the test circuit in Fig. 2b is used to extract τL . In the circuit, the clamp voltage Vclamp is 5 V, the capacitance C2 is 100 mF, and the gate resistor Rg2 is varied to change the anode voltage rise time.

The turn-off test is carried out at 5 V/50 A. On the basis of the simulated tail current, the current decay rate is calculated, as shown in Fig. 7. In the range in which the maximum current decay rate is approximately independent of the anode voltage rise time, is extracted to be 4.26 μs . By substituting the extracted into (19), τL is calculated to be 6.23μs .

Fig. 7.Current decay rate versus total current for PT IGBT.

The actual τL and τH of the PT IGBT device model are 6.3μs and 28ns , respectively. The extracted τL and τH show great accuracy.

C. Extraction for FS IGBT models

For the high clamp voltage extraction of the FS IGBT, the circuit in Fig. 2(a) is used to extract τH . All parameters in the circuit are the same as those used for the high clamp voltage extraction of the PT IGBT. The maximum current decay rate is determined, and τH is then extracted with (25). The extracted τH is plotted versus various clamped voltages in Fig. 8.

Fig. 8.Extracted τH versus clamp voltage for FS IGBT.

For the low clamp voltage extraction, the turn-off test is simulated at 5 V/50 A with the circuit in Fig. 2b. In the circuit, the capacitance C2 is 100 mF. The gate resistor Rg2 is varied to change the anode voltage rise time. On the basis of the simulated tail current, the current decay rate is extracted (Fig. 9). In the range in which the maximum current decay rate is independent of the anode voltage rise time, equal to the maximum current decay rate ( 4.35μs ). By substituting to (28), τL is extracted to be 5.6μs .

Fig. 9.Current decay rate versus total current for FS IGBT.

The actual τL and τH obtained from the FS IGB T device model are 6μs and 1μs , respectively. The extracted τL and τH are very close to the actual value.

The extracted τH is greatly overestimated when the extraction method for the PT IGBT is used to extract the lifetime, as shown in Fig. 9. This overestimation is caused by the FS layer being in a high-level injection condition [5] and the PT buffer layer being in a low-level injection condition; moreover, the lifetime of the high-level injection is longer than that of the low-level injection.

 

V. CONCLUSION

A novel excess carrier lifetime extraction method is proposed in this work. Compared with published extraction methods, the proposed method is novel in the following aspects.

(1) The newly proposed IGBT modeling method is used to derive a new excess lifetime extraction theory.

(2) The 2D Sentaurus numerical simulation is performed to validate the proposed method. In the validation, the actual excess carrier lifetime of the 2D numerical device model is obtained. The proposed method is then directly verified by the comparison of the extracted and actual lifetime.

In the end, the good agreement between the actual carrier lifetime and the extracted value demonstrates the accuracy of the proposed extraction method.

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