I. INTRODUCTION

For decades, the matrix converter (MC) has been an attractive topology for three-phase AC-AC power conversion [1]-[3]. The main reason for this interest lies in the potential advantages of MCs, such as bi-directional power flow, flexible input power factor, and no large energy storage elements. These superior features have resulted in the extensive attention being paid to MCs.

The modulation strategy is a pivotal factor that impacts on the performance of any converter. The existing modulation methods for MCs are intrinsically based on the well-known pulse-width modulation (PWM) [4]. As a result of such PWM switching pattern, MCs generate staircase-like high frequency common-mode voltage (CMV) waveforms. Unfortunately, large magnitude CMVs together with their high frequency variations are thought to be one of the important reasons for early winding failure and motor bearing deterioration [5].

To mitigate the CMV of MCs, several methods have been reported in literature. A common-mode canceler that acts similar to an active filter has been proposed [6]. Dual structure converters are applied to either direct- and indirect-MC-fed open-end winding drives to further reduce or eliminate the CMV output [7]-[10]. However, these methods need additional devices that increase the costs and thus are not considered in this paper.

Another method to alleviate the CMV issue is to modify the modulation strategies. Two active vectors with opposite directions [11]-[14] or three nearest-state vectors [13], [14] are used to replace zero vectors with high CMVs. These methods use more than five vectors, which increases the switching count. In addition, modulation strategies using the three nearest vectors that are adjacent to the reference vectors can only be applied in applications with high voltage transfer ratio (VTR) above 0.667. In order to reduce the switching count, Hong-Hee Lee et al. proposed strategies using two vectors with a 120◦ phase shift [15], [16]. However, this strategy can be only applied in applications with a low VTR below 0.5.

The switch states that connect each input line to a different output phase and have zero output CMV are not well explored in the aforementioned modulations. The difficulty of including them in the modulation process might account for the fact that they are not widely used. Ren Vargas et al. added a term in the quality function of their predictive current model to control the CMV [17]-[20]. Unforturntely, this method has a high computational overhead. Yugo Tadano et al. tried to use these switch states [21], [22]. However, this was done at the cost of a complex switch pattern selection.

This paper presents a CMV-reduced modulation for direct matrix converters based on the singular value decomposition (SVD) on all of the valid switch states [23]-[25]. First, the relationships between the different switch states are found. Then the OSSs are introduced by equivalent substitution. With part of the CMV waveforms being suppressed to zero, the proposed method decreases both the peak value and the root mean square (RMS) of the CMV. Because of its similarity, the proposed method has almost the same computation overhead as the conventional space vector modulation (SVM) method. The proposed method can also synthesize the reference variables without measurement of the output currents, which reduces costs.

Another contribution of this paper lies in that it provides an insight into the switch states of MCs by applying the SVD to the space vector representation of transfer functions. The SVD results in a set of sub-matrices for all of the valid switch states. Since the geometrical meanings of the SVD can help reveal the fundamental characteristics on how each switch state transforms a column vector between two different coordinates, this treatment offers a new basis for interpreting the modulation process.

II. SINGULAR VALUE DECOMPOSITION BASED SPACE VECTOR MODULATION

A. Matrix Converter System Model

The three-phase direct MC consists of a nine-switch array, as shown in Fig. 1. If the switches are modeled as ideal switching functions, the voltage relationship between both sides of the MC can be expressed as follows [23]–[26]:

where the transfer function S is the switch state matrix (SSM), representing the connection of the MC array. Similarly, the current relationship can be formulated as Ii = STIo , where the superscript “T” refers to the transposition operation. Typically, the converter connects both the voltage source and the current source. Consequently, only 27 switch state patterns are valid for safe operation.

Fig. 1.Three-phase direct matrix converter Configuration.

In the existing modulation methods, the SSMs are considered together with the input voltages and output currents to get the resultant vectors before the duty cycles are determined. However, even if the inputs are ideal, either the amplitudes or the angles of the resultant voltage or current vectors fluctuate [27]. This brings difficulties to the determination of the duty cycles. Actually, SSMs preserve the intrinsic characteristics of MCs, regardless of variations of the inputs. Therefore, this paper considers the SSMs and the system inputs separately, and starts from the voltage relationship. In order to simplify the analysis, Equ. (1) is transformed into its space vector representation, i.e. Vo,αβ0 = TST-1Vi,αβ0 , from the abc coordinates into the α-β reference frame by:

No zero sequence current flows in three-phase-three-wire systems. Therefore, ignoring the zero-sequence component, the voltage relationship can be expressed in matrix form [23]:

where Sxyz is the space vector form of the transfer matrix S in Equ. (1), and xyz represents the input phases that connect to the output phases. For example, when the output phases ABC connect to the input phases in the order of abb, Sxyz can be written as Sabb. Here the input and output voltage space vectors are = Viα + jViβ, = Voα + jVoβ, respectively.

B. Singular Value Decomposition of the Space Vector Transfer Matrix for All of the Valid Switch States

To reveal how the transfer function matrix transforms the input voltage column vector to the output voltage column vector, Sxyz in Equ. (3) is factorized by the SVD method into the multiplication of three matrices. This is represented as Sxyz = U∗D∗VT , where U and V are unitary matrices and D is a diagonal matrix, with σd and σq being the diagonal elements. These SSMs can be categorized into three types according to their SVD results, as listed in Table I.

TABLE I1 xxx means aaa, bbb or ccc.

1) Type I Switch States: These switch states have zero output line voltages and result in zero voltage space vectors by connecting all of the outputs to one input phase. For this type of SSM, the diagonal elements in the matrices Ds are all zero.

2) Type II Switch States: These switch states connect two and only two output phases to one input phase. They have a common feature since all of their factorized Us and Vs are rotation matrices. It is important to point out that the rotation angles of Us and Vs are determined only by the switch states, and are independent of the input voltages. If these rotation matrices are represented by their corresponding rotation vectors with the same effective angles, two hexagons with unit radius at the input and the output sides respectively, can be obtained in Fig. 2. Both hexagons are actually different from those in the traditional SVM, where the resultant voltage or current space vectors of the switch states together with the input voltages or output currents have fixed angles but variable amplitudes [27]. The type II switch states are also summarized in Table II, with the rotation angles of their decomposed Us and Vs matching the positions of their equivalent rotation vectors in both of the hexagons in Fig. 2.

Fig. 2.Space vector syntheses in input and output hexagons.

TABLE IISWITCH STATES ARRANGED ACCORDING TO FiG. 2

3) Type III Switch States: Corresponding to the traditional SVM, the last six switch states listed in Table I result in rotating output voltage space vectors with a fixed amplitude since the unitary matrices are isometry, but with variable angles depending on both the switch states and the inputs. The matrices Ds of this type of SSMs are the Identity Matrices.

C. Singular Value Decomposition based Traditional Space Vector Modulation

Suppose the desired transfer function is:

where Ū , are the local-averaged values of U, D, and V with respect to their duty cycles, α and β are the angles of Ū and , and gd and gq are the local-averaged axial gains. It is easy to synthesize these matrices using the first two types of switch states [23]. Since σq ≡ 0, the q-axis averaged gain gq is equal to zero. Hence, the output voltage reference is always located in the d-axis of the matrix Ū , while the input current reference is placed in the d-axis of the matrix , as shown in Fig. 3. Denoting both equivalent direction reference space vectors in Fig. 2, the continuously rotating Ū and can be approximated by two adjacent rotation vectors. Therefore, four Type II switch states and one Type I switch state are selected in accordance with the locations of the reference vectors. For example, when both the input and output reference quantities lie in Sector I, since the vectors pointing to (1), (2) and ⑥ , ① are used, taking into account the mutual match between the vectors shown in Fig. 2 and the SSMs listed in Table II, the switch states Sabb, Saab, Sacc and Saac are selected. Their duty cycles and the duty cycle for the zero vector are calculated to synthesize the local-averaged matrices Ū , :

where αsv and θsc are the angles of the reference vectors with respect to the beginning of their corresponding sectors, and the modulation index m is used to adjust the amplitude of the output voltages. The only limitation for m is to maintain the duty cycles in Equ. (5) as nonnegative.

Fig. 3.Geometrical relationships between the input and output quantities.

The switching sequences among the different switch states are arranged, where one zero switch state is employed, as shown in Fig. 4 [28]. When the sum of the two sector numbers is even, a “u” shape switching pattern is utilized. Otherwise, if the sum of the two sector numbers is odd, an “n” shape pattern is used.

Fig. 4.Switching sequence pattern selection.

III. COMMON-MODE VOLTAGE REDUCED SPACE VECTOR MODULATION

For motor drive systems it is important to reduce the CMV generated by their power converters. Since it is common to connect the motor frame to the ground, the leakage current due to the CMV flows through the parasitic capacitor coupling to the rotor. High leakage currents can lead to early failures of the winding insulation and motor bearings. In that the sum of the output currents approaches zero, the CMV then becomes:

The peak values of the CMV for the three types of switch states are calculated as [29]:

where vim is the amplitude of the input phase voltage. As can be seen, the Type III switch states have preference over the others, despite the fact that they are not well explored. Since the CMV depends on the switch states of the converter, it is preferable to choose those states with a low CMV magnitude and low voltage transitions whenever possible.

A. Principle of Replacement

Note that there exists an interesting relationship between the SSMs of the last two types of switch states. This relationship is expressed in the following equations:

Each Type III switch state is equivalent to two different switch state couples, each of which contains two Type II switch states. Once both of the switch states can be obtained, it is possible to replace them with their Type III equivalent, which curtails that part of the CMV to zero.

To start with, one of the Type III switch states that rotates the input voltage space vector to the sector of the output voltage space vector is selected, as summarized in Table III. Here the sector division for is the same as that for rather than that for the input current space vectors. This means that the range from 0 to 60◦ in the complex plane is the first sector for .

TABLE IIISELECTION OF THE ORIENTATION SWITCH STATES

Once the Type III switch state is chosen, the next step is to find its Type II equivalents. As can be seen from Equ. (8), one switch state within each couple is always contained in the four switch states that are selected by the traditional SVM. As discussed in Section II-C, four switch states, any two of which share one direction vector in at least one hexagon, can synthesize two vectors in the input hexagon and two vectors in the output hexagon. According to the directions of these coupled switch states, two more supplementary switch states can be picked up to synchronously make two direction vectors in both hexagons. Then these two vectors can be used to synthesize the rotational Ū and . This can be done together with other active vectors if needed. After the duty cycles for all of the required switch states are calculated, the corresponding Type II switch states can be combined as their equivalent Type III switch state.

Within both switch state couples of the Type III switch state, only one is used in this work to reduce the switching number. The one whose combined effective vectors are close to both Ū and is selected for the extended replacement.

B. Example

For convenience, the proposed algorithm is evaluated for the case that the input voltage space vector and the reference vectors Ū and are all located in Sector I. Four switch states Sabb, Saab, Sacc and Saac have been chosen by the conventional SVM as discussed in Section II-C.

Since the input and output voltage vectors are located in the same sector, the Type III switch state Sabc is selected. Then two switch state couples Sabc = Sacc + Scbc and Sabc = Sabb + Sbbc are possible for substitution. For the former couple, the Type II switch state Sacc points to vector (1) in the input hexagon and vector ① in the output hexagon while Scbc points to (3) and ② , respectively. The vectors pointing to (1), (3) and ① , ② are selected for synthesizing. Since only Sacc is within the four chosen switch states, three more switch states Scbc, Scac and Sbcc are needed to synthesize the blue vectors shown in Fig. 5. The last two switch states point to (3)① and (1)② . On the other hand, the latter couple needs two more switch states Sbcc and Sbbc which direct to (1)② and (2)② to synthesize the blue vectors shown in Fig. 6. This is because the switch states Sabb and Saab pointing to (1)⑥ and (2)⑥ are already within the four chosen Type II switch states. For the former couple, the resultant direction vector at the input hexagon is in Sector II, which is different from that of ; while for latter couple the resultant vectors at both hexagons are in the same sectors where the references Ū and located. Thus, Sabc = Sabb + Sbbc is chosen.

Fig. 5.Synthesis scheme for Combination Sabc = Sacc + Scbc.

Fig. 6.Synthesis scheme for Combination Sabc = Sabb + Sbbc.

It should be noted that the duty cycles for the switch states in Equ. (8) are equal. The switch states to make up the blue vector shown in Fig. 6, i.e. Sabb, Saab, Sbcc, and Sbbc, share the same duty-cycle with the Sabc. Thus, the maximum duty-cycle for the Type III switch state in the proposed method depends on the minimum duty cycles for its two equivalent switch states, i.e. Sabb and Sbbc. In other words, it depends on the position of Ū in this case, because the blue vector shown in the input hexagon of Fig. 6 points to ① .

If Ū is in the first half of its sector, the maximum duty-cycle for Sabc is dβdγ, which is the duty-cycle for the switch state Saac, or the vectors pointing to both (2) and ①. The switch state Saac is not needed any more since its effect has been replaced by the switch states Saab and Sbbc. To complete the vectors pointing to both (1) and ① synchronously, the rest duty-cycle (dμ − dγ )dβ has to be conducted by the switch state Sacc, as shown in Fig. 7. So far, five Type II switch states have been chosen. The rest of the switching period is for zero vectors that can be implemented by a pair of Type II switch states with reverse directions, i.e. Sbab and Saba. Since all of them share the same σq ≡ 0, the same modulation index m can be multiplied to the transfer function matrices for all of the switch states used to regulate the amplitude of the output voltages. In the end, the Type II switch states Sabb and Sbbc with same duty-cycle can be combined as their equivalent Type III switch state Sabc. The used switch states together with their duty cycles and switching sequence pattern can be found in Table IV.

Fig. 7.Vector Synthesis when Ū is in the first half sector.

TABLE IVSWITCHING PATTERN IF Ū IS IN THE 1ST HALF SECTOR

Similarly, if Ū is in the second half of its sector, then the maximum duty-cycle for Sabc is dαdγ, as shown in Fig. 8. The switch state Sacc disappears since its effect is replaced by the switch states Sabb and Sbcc. The rest of the vector pointing to both (2) and ① is performed by the switch state Saac with the duty cycle (dα−dβ)dγ. Two pairs of Type II switch states with reverse directions are selected to replace the zero vector for the switching sequence arrangement, which is slightly different from the case where Ū is in the first half sector. The duty cycles and the switching sequence pattern for the selected switch states can be found in Table V.

Fig. 8.Vector Synthesis when Ū is in the last half sector.

TABLE VSWITCHING PATTERN IF Ū IS IN THE 2ND HALF SECTOR

IV. EXPERIMENT RESULTS

Experiments are carried out to verify the feasibility of the proposed algorithm. The switch array of the MC consists of twelve bi-directional insulated-gate bipolar transistor (IGBT) switch modules SK60GM123 from SEMIKRON. The control platform is composed of a development starter kit (DSK) 6713 and a field programmable gate array (FPGA) daughter board. The SVM algorithms are implemented using a Texas Instruments digital signal processor (DSP) TMS320C6713 on the DSK. A FPGA A3P400 from Actel is used to implement the four-step current commutation [30] and to generate the gate drive signals for the IGBT. The complete prototype system is shown in Fig. 9. Since there is a focus on CMV suppression in this work, the modulation index is fixed to avoid interference of constant power loads which will be introduced by the fast closed-loop control strategies or feed-forward compensation by modulations [31]. For the sake of simplicity, the input current modulation strategy is set to give the unit input power factor. The system parameters used are listed below:

1) a three-phase supply with a phase voltage RMS of 110V at 50Hz fundamental frequency; 2) an input filter inductor of 1mH, and an input filter capacitor of 9μF; 3) an output frequency of 30Hz; 4) a sampling frequency of 10kHz; 5) a three-phase RL load in a Y- type connection with Ro = 50Ω and Lo = 15mH.

Fig. 9.A four-leg direct matrix converter prototype with its control platform.

Fig. 10 shows waveforms for the converters with an index of m = 0.7. Both methods work well to keep the source and output currents sinusoidal. The peak value of the CMV is reduced by about 42% from 156V in Fig. 11(a) to 90V in Fig. 11(b). Note that a ringing effect can be observed in the CMV waveforms due to the inductor at the loads. This effect extends the peak-to-peak value of the CMV. However, even taking this effect into account, the proposed method has a smaller CMV peak than the conventional SVM. As can be observed from the detailed CMV waveforms shown in Fig. 11, parts of the instantaneous CMV in every switching period are reduced to zero when the proposed method is employed. However, this cannot be seen in the conventional SVM. The RMS of the CMV has also been decreased by 20.3% from 93.7V for the traditional SVM to 74.4V for the proposed SVM method.

Fig. 10.Waveforms for the MC with (a) the traditional SVM, (b) the proposed SVM employed, setting m = 0.7.

Fig. 11.Zoomed CMV waveforms with (a) the conventional SVM, (b) the proposed SVM, with modulation index as 0.7.

Similarly, experiments are carried out with a modulation index of m = 0.5, as shown in Fig. 12. As can be seen, both methods can generate sinusoidal output currents while maintaining good quality input currents. The experimental results also show that the proposed method is feasible for working in both high and low VTR applicatons. The CMV waveforms and their zoomed views are also given in Fig. 13. Similar peak value reduction, i.e. 42.3% can be achieved. Further, more reduction on the RMS of the CMV, up to 38.4% from 115.2V for the conventional SVM to 70.9V for the proposed method, can be obtained. Once again, the type III switch states that have zero CMV can be observed in every switch sequence of the proposed method from the zoomed view shown in Fig. 13(b).

Fig. 12.Waveforms for the MC with (a) the traditional SVM, (b) the proposed SVM employed, setting m = 0.5.

Fig. 9.Zoomed CMV waveforms with (a) the conventional SVM, (b) the proposed SVM, with modulation index as 0.5.

It should be noted that the maximum delays in the timer counts for the tranditional SVM and the proposed method are 4660 and 5010, respectively. With respect to the CPU clock rate, the maximum time consumption increases from 82.84μs to 89.06μs. However, this difference is negligible. Therefore, the proposed method needs a similar computational overhead as the tranditional SVM.

V. CONCLUSIONS

An SVM algorithm based on the SVD technique to reduce the high-frequency CMV at the output of matrix converters has been proposed. In comparison with the traditional SVM, the switch states that connect each output line to a different input line are included in the switching sequence by combining two of their equivalent switch states. The CMVs are suppressed to zero during the time intervals for the switch states that are not used in the traditional SVM methods. As much as a 42% reduction in the peak value and a 20.3% reduction in the RMS of the CMV can be achieved. Therefore, the proposed method outperforms the traditional SVM in generating a lower CMV.