I. INTRODUCTION

In recent years, high step-up DC-DC converters have been widely used in many renewable energy systems, such as fuel cells and photovoltaic panels. However, the output voltages of these renewable energy systems are not always stable, and they are not high enough to supply the output load or to be linked to an AC power grid via a DC-AC inverter [1]-[3]. Consequently, a high step-up converter is required to obtain a high output voltage. For non-isolated converters to be considered, traditional boost and buck-boost converters [4] are widely used because of their simple structures. However, achieving high output voltages with a moderate duty cycle is difficult because of the parasitic components of these converters. In addition, the switches must block high output voltages. Accordingly, switches with high on-resistance are required; thus, the conduction loss is high. Many non-isolated step-up converters using different voltage-boosting techniques have been presented to achieve high output voltages. These voltage-boosting techniques include coupled inductors [5]-[10], switched capacitors [11], [12], voltage multipliers [13], [14], etc. However, in some applications, isolated converters are preferred to meet the safety requirements of galvanic isolation [15]. Therefore, the traditional flyback converter is appealing in industrial applications because of its low component count, simple structure, and low cost. However, it suffers from low voltage gain. Therefore, a number of isolated step-up converters have been presented [16]-[18]. In [16], a converter integrating an active clamp flyback converter and a voltage multiplier is presented. However, the input current is pulsating, hence the high input current ripple. In [17], an isolated converter comprising a tapped inductor and isolated switched capacitor is presented. However, the voltage gain is not high enough, the voltage spike is considerably high, and the input current is pulsating. In [18], an isolated converter consisting of a boost converter and a series resonant converter is presented. Even though the input current is non-pulsating, this converter involves two stages and comprises six switches, which increase the complexity of the overall circuit and the number of drivers. In [19] and [20], a two-switch flyback is presented. An additional MOSFET switch and two additional diodes are added to the classic single-switch flyback converter to provide a recycling path for leakage inductance energy. Thus, the voltage spike can be clamped to the input voltage. In [21], an isolated high voltage-boosting converter derived from a forward converter is presented. An active clamp circuit is employed to reduce the voltage spike across the switch. However, the input current is pulsating; thus, this converter is not suitable for renewable energy applications. Moreover, this converter comprises four windings, and its selection of turn ratios is limited. Thus, designing a coupled inductor is difficult. In [22], an LC snubber used in a synchronously rectified flyback converter to clamp the switch voltage stress is presented because LC snubbers do not dissipate the energy theoretically and do not use any active switch. However, the input currents of the three aforementioned converters are pulsating. In renewable energy applications, DC-DC converters with a high voltage gain and non-pulsating input current are required. Therefore, in [23]-[26], non-isolated step-up converters featuring a continuous input current is presented. High step-up converters with a non-pulsating input current offers several advantages. First, the input current ripple is relatively small. Therefore, the life of the input capacitor can be upgraded. For high step-up converters with a pulsating input current, the input capacitor must absorb the high AC component of the input current. Second, a high input ripple may reduce the power outputted from the solar energy [27]. In [28], an isolated step-up converter featuring a continuous input current is presented.

As indicated by the discussion above, achieving a high output voltage necessitates a non-pulsating input current, galvanic isolation, and high efficiency. Thus, the present study proposes a novel isolated high step-up converter, which integrates a boost converter, a coupled inductor, a charge pump capacitor cell, and an LC snubber. In the proposed converter, the input current supplied from the source is continuous, a high voltage gain can be realized without a high turn ratio and a large duty cycle, the leakage inductance energy can be recycled to the output load, the voltage stresses across switches are low, and galvanic isolation exists between the input terminal and the output terminal.

 

II. PROPOSED TOPOLOGY

Fig. 1(a) shows the proposed converter, which is composed of one input inductor L1, one boost capacitor C1, one boost diode D1, one MOSFET switch S1, one coupled inductor T comprising a primary winding with Np turns and a secondary winding with Ns turns, two snubber diodes Dsn1 and Dsn2, one snubber inductor Lsn, one snubber capacitor Csn, two charge pump capacitors C2 and C3, two charge pump diodes D3 and D4, and one output capacitor Co. Fig. 2(b) shows the proposed converter with the snubber. Vi, Vo, and Ro denote the input voltage, output voltage, and output resistor, respectively.

Fig. 1.Proposed isolated step-up converter: (a) without snubber; (b) with snubber but without current and voltage symbols; (c) with snubber and with current and voltage symbols.

Fig. 2.Illustrated waveforms of the proposed converter in CCM for both L1 and Lm.

 

III. BASIC ANALYSIS OF THE PROPOSED CONVERTER

For ease of analysis, we derive a number of assumptions and adopt voltage and current symbols.

As shown in Fig. 1(c), the currents flowing through L1, D1, S1, Lm, and the windings Np and Ns are denoted by iL1, iD1, iDS1, iLm, iNp, and iNs, respectively. The currents flowing through Dsn1 and Dsn2 or Lsn, Csn, D2, D3, D4, Do, and Ro are denoted by iDsn1, iDsn2, iCsn, iD2, iD3, iD4, iDo, and io, respectively. Moreover, the voltages across L1, Lsn, Csn, and S1 are denoted by vL1, vLsn, vCsn, and vDS1, respectively. The voltages across Lm or Np, Ns, C1, C2, C3, and Co are denoted by vLm, vNs, VC1, VC2, VC3, and Vo, respectively.

The following analysis covers the (i) operating principles, (ii) voltage gain, (iii) boundary condition for the input inductor, (iv) boundary condition for the magnetizing inductor, and (v) comparison of the proposed converter, the converter in [21], and the quasi-resonant (QR) flyback converter.

A. Operating Principles

The proposed converter comprises eight operating modes, and the key waveforms are shown in Fig. 2. The gate driving signal vgs1 of the switch S1 has a duty cycle of D, where D is the DC quiescent duty cycle created from the controller.

1) Mode 1 [ t0 ≤ t ≤ t1 ]: During this interval [Fig. 3(a)], S1 is turned on, and D2 is forward-biased. The currents iD3 and iD4 continue charging C2 and C3, respectively. The voltage across Lm and vLm is a negative value, which is induced from the secondary winding Ns. Hence, Lm remains demagnetized. The voltage VC1 + (Np / Ns ) ×VC3 is imposed on Llk, thereby causing iLlk to increase rapidly. Furthermore, D1 becomes reverse-biased, Dsn2 becomes forward-biased, and Dsn1 remains reverse-biased. Therefore, the input voltage Vi is imposed on L1, thus causing L1 to be magnetized. Moreover, Csn releases energy to Lsn, thereby causing Csn and Lsn to resonate during a positive cycle. Do remains reverse-biased; hence, only Co supplies energy to the load. This mode ends when iLlk is equal to iLm at t=t1.

Fig. 3.Power flow paths over one switching period in CCM. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8.

2) Mode 2 [ t1 ≤ t ≤ t2 ]: During this interval [Fig. 3(b)], S1 is still turned on, D3 and D4 become reverse-biased, and Do becomes forward-biased. Therefore, C1, C2, and C3 provide energy to the load. Meanwhile, the voltage VC1 is imposed on Lm and Llk, thus causing their continuous magnetization. Moreover, the energy stored in Csn is continuously released to Lsn until vCsn reaches zero. Thereafter, the energy stored in Lsn is released to charge Csn. As a result, the voltage across Csn and vCsn increases in the opposite direction. This mode ends when vCsn reaches -VC1 at t=t2.

3) Mode 3 [ t2 ≤ t ≤ t3 ]: During this interval [Fig. 3(c)], S1 is turned on; D1, D3, and D4 are reverse-biased; and Dsn2 and Do are forward-biased. The voltage across the snubber capacitor vCsn is clamped to -VC1 . Moreover, the diode Dsn1 is forced to conduct by the current from Lsn. Therefore, the energy stored in Lsn is transferred to the output load via the coupled inductor. This mode ends when the energy from Lsn drops to zero, i.e., iDsn2 reaches zero at t=t3.

4) Mode 4 [ t3 ≤ t ≤ t4 ]: During this interval [Fig. 3(d)], S1 is turned on; D1, D2, and D3 are reverse-biased; and Do is forward-biased. After iDsn2 reaches zero, the diodes Dsn1 and Dsn2 become reverse-biased. This mode ends when S1 is turned off at t=t4.

5) Mode 5 [ t4 ≤ t ≤ t5 ]: During this interval [Fig. 3(e)], S1 is turned off, but C2, C3, and the coupled inductor continue to supply energy to the load. Moreover, the energy stored in L1 is released to C1 via D1, and the leakage inductance current iLlk charges the snubber capacitor Csn via Dsn1 and the parasitic capacitor Cds1. Therefore, vCsn increases linearly from -VC1 . This mode ends when iNs reaches zero at t=t5.

6) Mode 6 [ t5 ≤ t ≤ t6 ]: During this interval [Fig. 3(f)], S1 is turned off. The only difference between the previous mode and the current mode is that the energy stored in the magnetizing inductor Lm is transferred to C2 and C3, which are connected in parallel via D3 and D4. Meanwhile, the output diode Do becomes reverse-biased. Therefore, only the output capacitor Co provides energy to the load. Moreover, the leakage inductance current iLlk continuously releases energy to the snubber capacitor Csn, thereby causing vCsn to increase gradually. The voltage across S1 also increases and becomes equal to VC1 + vCsn . This mode ends when iLlk reaches zero at t=t6.

7) Mode 7 [ t6 ≤ t ≤ t7 ]: During this interval [Fig. 3(g)], S1 is turned off. The snubber capacitor voltage vCsn reaches the maximum value, which is higher than VC1 +VC2 / n . Consequently, the diode Dsn2 becomes forward-biased. Therefore, the energy stored in Csn is discharged to C1 and the secondary side. During this period, Lm is clamped to -VC3 ‧ (Np / Ns ) . Moreover, the snubber capacitor Csn, snubber inductor Lsn, and leakage inductor Llk resonate together. This mode ends when iDsn2 reaches zero at t=t7.

8) Mode 8 [ t7 ≤ t ≤ t0 ]: During this interval [Fig. 3(h)], S1 remains turned off. With iDsn2 reaching zero, Dsn2 becomes reverse-biased. Moreover, Lm continuously delivers energy to charge C2 and C3. Therefore, iLm decreases gradually. During this period, the voltage across Llk is zero. Thus, the voltage stress of S1 is VC1 + (Np / Ns ) ‧VC3 . This mode ends when S1 is turned on at t=t0. The next cycle is subsequently repeated.

B. Voltage Gain

Only Figs. 3(b) and (f) are considered, and the leakage inductor Llk and LC snubber are ignored to obtain the voltages across C1, C2, and C3, as well as the voltage gain. The voltages across L1 and Lm, as shown in Fig. 3(b), are written as follows:

The voltages across L1 and Lm, as shown in Fig. 3(f), are written as follows:

First, by applying the voltage–second balance principle to L1 over one switching period, the following equation can be obtained:

By rearranging the above equation, the voltage across C1 can be obtained as

Second, by applying the voltage–second balance principle to Lm over one switching period, the following equation can be obtained:

By rearranging the above equation, the voltages across C2 and C3 can be obtained as

On the basis of Fig. 3(b), the output voltage can be determined as follows:

The corresponding voltage gain can be expressed as

Fig. 4 shows the curves of the voltage gain versus the duty cycle of the proposed converter with different turn ratios considered.

Fig. 4.Curves of voltage gain versus duty cycle of the proposed converter with different values of turn ratio n.

C. Boundary Condition for Input Inductor

The condition for the magnetizing inductor L1 operating in a specific region is described as follows:

where IL1 and ΔiL1 are the DC and AC components of iL1, respectively.

For ease of analysis, we assume that the input power is equal to the output power. Therefore, the input current IL1 can be expressed as

Substituting Vo / Ro into Io in (12) yields the following equation:

Moreover, ΔiL1 can be written as

Given that 2IL1 ≥ ΔiL1 , L1 operates in the CCM. The further deduction is shown as follows:

where and

Based on (15), the relationship between Kcrit1(D) and D is shown in Fig. 5 under the condition that n is set to 3. As shown in Fig. 5, L1 operates in CCM if K1 is larger than Kcrit1(D) ; otherwise, L1 operates in DCM.

Fig. 5.Boundary condition for the input inductor L1.

D. Boundary Condition for Magnetizing Inductor

The condition for the magnetizing inductor Lm operating in a given region is described as follows:

where ILm and ΔiLm are the DC and AC components of iLm, respectively.

The expression of ILm can be derived from (17) to (20). For ease of analysis, we assume that the input power is equal to the output power. According to the voltage–second balance principle for inductors and the ampere–second balance principle for capacitors, the DC component of the inductor voltage and the DC component of the capacitor current are both zero over one switching period in the steady state.

Therefore, as shown in Fig. 6(a), the DC component of iNs and INs is equal to the output current Io. Similarly, the DC component of iLm and ILm is equal to the current Ix entering the primary side of the coupled inductor plus the DC component of iNp and INp (Figs. 6(a) and (b)). Therefore,

Fig. 6.DC component: (a) marked areas in the proposed converter used to analyze ILm; (b) equivalent model for the DC analysis of the coupled inductor.

On the basis of (13) and (17), Ix can be derived as

In addition, ΔiLm can be written as

As 2ILm ≥ ΔiLm , Lm operates in CCM. The further deduction is shown as follows:

where and

Based on (22), the relationship between Kcrit2 (D) versus D is shown in Fig. 7 under the condition that n is set to 3. As shown in Fig. 7, Lm operates in CCM if K2 is larger than Kcrit2 (D) ; otherwise, Lm works in DCM.

Fig. 7.Boundary condition for the magnetizing inductor Lm.

E. Comparison of the Proposed Converter, the Converter in [21], and the QR Flyback Converter

With the snubber disregarded, the proposed converter is compared with the converter in [21] and the quasi-resonant flyback converter (Table I).

TABLE ICOMPARISON OF THE PROPOSED CONVERTER, THE QR FLYBACK CONVERTER, AND THE CONVERTER IN [21]

Table I shows that the voltage gain of the converter in [21] can be determined by the duty cycle and four windings N1, N2, N3, and N4. However, the selection of turn ratios is limited, that is, N4 > N3 - N2 . The design procedure of the coupled inductor of the converter in [21] is more complicated than that of the proposed converter. Furthermore, the proposed converter entails a continuous input current and is thus suitable for renewable energy applications. The converter in [21] includes an output inductor; hence, the voltage gain is low. Therefore, in comparison with the proposed converter, the converter in [21] achieves a higher duty cycle and turn ratio. When voltage stress is considered, the duty cycle can be relatively short because the voltage gain of the proposed converter is high. Thus, voltage stress can be maintained at a low value.

Table I also shows the details of the QR flyback converter. Its voltage gain is much lower than that of the proposed converter. Thus, to achieve a high voltage gain, the flyback converter requires a high duty cycle and a high turn ratio. Moreover, it is often used in low-power applications. The MOSFET switch can be turned on at its voltage valley to reduce the switching loss resulting from the QR control [29]. For conduction loss to be considered, the component characteristics, component count, and root mean square (RMS) must be taken into account. The flyback converter exhibits a smaller component count than the proposed converter. For the flyback converter to achieve the same voltage gain as the proposed converter, its duty cycle and turn ratio should be significantly larger. In such a case, current stress and the resistance of the coupled inductor become considerably high. In comparison with the flyback converter, the proposed converter exhibits a much higher voltage gain, hence the minimal duty cycle and turn ratio that it requires.

 

IV. DESIGN CONSIDERATIONS

To verify the effectiveness of the proposed converter, we build and test a prototype. Tables II and III show the specifications and components of the proposed converter, respectively.

TABLE IISPECIFICATIONS OF THE PROPOSED CONVERTER

TABLE IIICOMPONENTS USED IN THE PROPOSED CONVERTER

The design procedures for the input inductor L1, magnetizing inductor Lm, and LC snubber [22] are described as follows.

A. Inductor Design

1) Input Inductor Design: To ensure that the input inductor current iL1 is always in CCM, we derive the corresponding equations as follows:

where IL1,min is the minimum DC current in L1. Hence, the value of L1 is set to 40 μH.

Based on (15) and the parameters selected for the proposed converter, the input inductor current iL1 is under CCM when the output current Io is higher than 0.0436 A, which is calculated in (25). When the output current Io is lower than 0.0436 A, the input inductor current iL1 enters into DCM.

Finally, the current ripple of iL1 is shown in (26).

2) Magnetizing Inductor Design: To ensure that the magnetizing inductor current iLm is always in CCM, we write the corresponding equations as follows:

where ILm,min is the minimum DC current in Lm. Hence, the value of Lm is set to 51 μH.

Based on (22) and the parameters selected for the proposed converter, the magnetizing inductor current iLm is under CCM when the output current Io is higher than 0.0948 A, which is calculated in (29). When the output current Io is lower than 0.0948 A, the magnetizing inductor current iLm enters into DCM.

Finally, the current ripple of iLm is shown in (30).

B. LC Snubber Design

The voltage spike is severe when the output load is rated. Hence, the LC snubber is designed at a rated load (CCM for both L1 and Lm).

1) Snubber capacitor design: The energy stored in the primary-side leakage inductance Llk during the turn-on period is

The energy stored in the snubber capacitor is

If the primary-side leakage inductance energy is released entirely to the snubber capacitor, then the following equality can be obtained:

Based on (31), (32), and (33), the value of the snubber capacitor can be determined as follows:

where iLlk,max is the maximum leakage inductance current, iLlk,min is the minimum leakage inductance current, vCsn,max is the maximum voltage across Csn, and vCsn,min is the minimum voltage across Csn (Fig. 8).

Fig. 8.Waveforms for designing the LC snubber for both L1 and Lm operating in CCM.

In mode 2 [Fig. 3(b)], vCsn,min is clamped to -VC1 . In mode 5 [Fig. 3(e)] and mode 6 [Fig. 3(f)], ΔvCsn is identical to ΔvDS1 . Therefore, vCsn,min can be obtained as follows:

In mode 5 [Fig. 3(e)] and mode 6 [Fig. 3(f)], ΔvCsn is identical to ΔvDS1 . Accordingly, the maximum spike voltage of vDS1 is assumed to be 60 V because of the leakage inductance. Therefore, vCsn,max can be obtained as follows:

Based on (34), the value of the snubber capacitor can be determined as follows:

Finally, two 22 nF film capacitors connected in parallel are chosen for Csn.

2) Snubber inductor design: The snubber inductance Lsn can be estimated by using the following equation:

If the resonance frequency of the LC snubber is assumed to be twice the switching frequency, then the snubber inductance can be obtained as follows:

Finally, the value of Lsn is set to 15 μH.

 

V. EXPERIMENTAL RESULTS

Figs. 9 and 10 show the measured waveforms at a rated load. Fig. 9 shows the gate driving signal for S1, vGS1; the voltage across S1, vDS1; and the input current, iL1. Fig. 10 shows the gate driving signal for S1, vGS1; the current flowing through Llk, iLk; and the secondary side current, iNs.

Fig. 9.Waveforms at a rated load: (1) vGS1; (2) vDS1; (3) iL1.

Fig. 10.Waveforms at a rated load: (1) vGS1; (2) iLk; (3) iNs.

Fig. 9 shows that the spike voltage of vDS1 is clamped at 56 V and that the voltage stress without a spike is about 45 V, which is approximately equal to the calculated value of Vo/[n(1+D)] ≈ 44.9V. The input current is continuous, and its peak-to-peak current value is about 1.5 A. Fig. 10 shows that during the turn-off period of S1, iNs is a negative current, which matches the waveform of iLlk shown in Fig. 2.

Figs. 11 and 12 show the measured waveforms at a light load. Fig. 11 shows the waveforms of vDS1 and iL1. At a light load, iL1 enters into DCM. The voltage spike is low, and the voltage stress without a spike is about 45 V. As a result of the entry to DCM, a resonance voltage is noted across vDS1. This effect is attributed to Lm and Llk resonating with Cds1. Fig. 12 shows iLk and iNs. Here, ilk is low at a light load. Therefore, when S1 is turned off, the voltage spike becomes considerably low.

Fig. 11.Waveforms at a light load: (1) vGS1; (2) vDS1; (3) iL1.

Fig. 12.Waveforms at a light load: (1) vGS1; (2) iLk; (3) iNs.

Fig. 13 shows the curve of efficiency versus the load current. The efficiency across the load range ranges from 82% to 89%, whereas the rated load efficiency is about 85%.

Fig. 13.Efficiency versus load current.

 

VI. CONCLUSION

An isolated high step-up converter with continuous input current is presented. The proposed converter comprises a boost converter, a coupled inductor, and a charge pump capacitor cell. Hence, a high step-up voltage gain can be achieved with a relatively low duty cycle. Moreover, the leakage inductance energy can be recycled to the output capacitor of the boost converter with the LC snubber and then transferred to the output load. Therefore, the voltage spike of the switch can be clamped at a low value, and the switch with a low turn-on resistance can be used. In doing so, efficiency is improved. The operating principle analyses, designs, and experimental results are provided to verify the effectiveness of the proposed converter.