Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Reliability Characteristics of a Package-on-Package with Temperature/Humidity Test, Temperature Cycling Test, and High Temperature Storage Test

온도/습도 시험, 온도 싸이클링 시험 및 고온유지 시험에 따른 Package-on-Package의 신뢰성

  • Park, Donghyun (Department of Materials Science and Engineering, Hongik University) ;
  • Oh, Tae Sung (Department of Materials Science and Engineering, Hongik University)
  • 박동현 (홍익대학교 공과대학 신소재공학과) ;
  • 오태성 (홍익대학교 공과대학 신소재공학과)
  • Received : 2016.09.12
  • Accepted : 2016.09.27
  • Published : 2016.09.30
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Abstract

Reliability characteristics of thin package-on-packages were evaluated using T/H (temperature/humidity) test at $85^{\circ}C/85%$ for 500 hours, TC (temperature cycling) test at $-40{\sim}100^{\circ}C$ for 1,000 cycles, and HTS (high temperature storage) test at $155^{\circ}C$ for 1,000 hours. The average resistance of the solder-bump circuitry between the top and bottom packages of 24 package-on-package (PoP) samples, which were processed using polyimide thermal tape, was $0.56{\pm}0.05{\Omega}$ and quite similar for all 24 samples. Open failure of solder joints did not occur after T/H test for 500 hours, TC test for 1,000 cycles, and HTS test for 1,000 hours, respectively.

박형 package-on-package에 대해 T/H (temperature/humidity) 시험, TC (temperature cycling) 시험과 HTS(high temperature storage) 시험을 사용하여 신뢰성을 분석하였다. T/H 시험은 $85^{\circ}C/85%$의 조건으로 500시간, TC 시험은 $-40{\sim}100^{\circ}C$의 조건으로 1000회, HTS 시험은 $155^{\circ}C$의 조건으로 1,000시간 범위에서 평가하였다. 폴리이미드 써멀테이프를 사용하여 제작한 24개의 package-on-package (PoP) 시편에 대해 신뢰성 시험 전에 측정한 솔더접속 배선의 평균저항은 $0.56{\pm}0.05{\Omega}$이었으며, 24개 시편에서 모두 유사한 값이 측정되었다. 500시간까지의 T/H 시험, 1000회의 TC 시험 및 1,000시간까지의 HTS 시험후에도 솔더 접속부의 오픈 불량은 발생하지 않았다.

Keywords

References

  1. D. H. Park, S. J. Shin, S. G. Ahn and T. S. Oh, "Warpage Analysis for Top and Bottom Packages of Package-on-Package Processed with Thin Substrates", J. Microelectron. Packag. Soc., 22(2), 61 (2015). https://doi.org/10.6117/kmeps.2015.22.2.061
  2. J. L. Leila, "Numerical Analysis of Thermomechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-dimensional Integrated Circuits", Microelectron. Eng., 87(2), 208 (2010). https://doi.org/10.1016/j.mee.2009.07.022
  3. D. H. Park, D. M. Jung and T. S. Oh, "Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps", J. Microelectron. Packag. Soc., 21(2), 65 (2014). https://doi.org/10.6117/kmeps.2014.21.2.065
  4. N. Vijayaragavan, F. Carson and A. Mistry, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 389, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  5. H. Eslampour, Y. C. Kim, S. W. Park, T. and W. Lee, "Low Cost Cu Column fcPoP Technology", Proc. 62nd Electronic Components and Technology Conference (ECTC), San Diego, 871, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2012).
  6. F. Roa, "Very Thin PoP and SIP Packaging Approaches to Achieve Functionality Integration prior to TSV Implementation", Proc. 64th Electronic Components and Technology Conference (ECTC), Orlando, 1656, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2014).
  7. C. G. Kim, H. S. Choi, M. S. Kim and T. S. Kim, "Packaging Substrate Bending Prediction due to Residual Stress", J. Microelectron. Packag. Soc., 20(1), 21 (2013). https://doi.org/10.6117/kmeps.2013.20.1.021
  8. J. Zhao, Y. Luo, Z. Huang and R. Ma, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1081, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  9. C. H. Chien, Y. C. Chen, Y. T. Chio, T. Chen, C. C. Hsieh, J. J. Yan, W. Z Chen and Y. D. Wua, "Influences of the Moisture Absorption on PBGA Package's Warpage during IR Reflow Process", Microelectron. Reliab., 43(1), PI-1388131 (2003).
  10. M. J. Yim, R. Strode, R. Adimula, J. J. Zhang and C. Yoo, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1141, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011).
  11. http://www.standardsys.co.kr/main/img/VTEC_1388_Liquid_110706.pdf
  12. JESD22-A101C, "Steady State Temperature Humidity Bias Life Test", JEDEC Solid State Technology Association, Electronic Industries Alliance, Arlington (1997).
  13. JESD22-A104D, "Temperature Cycling", JEDEC Solid State Technology Association, Electronic Industries Alliance, Arlington (2009).
  14. JESD22-A103C, "High Temperature Storage Life", JEDEC Solid State Technology Association, Electronic Industries Alliance, Arlington (2004).
  15. R. A. Gagliano and M. E. Fine, "Thickening Kinetics of Interfacial Cu6Sn5 and Cu3Sn Layers during Reaction of Liquid Tin with Solid Copper", J. Electron. Mater. 32, 12 (2003).
  16. T. Y. Lee, W. J. Choi, K. N. Tu, J. W. Jang, S. M. Kuo, J. K. Lin, D. R. Frear, K. Zeng and J. K. Kivilahti, "Morphology, Kinetics, and Thermodynamics of Solid-State Aging of Eutectic SnPb and Pb-free Solders (Sn-3.5 Ag, Sn-3.8 Ag-0.7 Cu and Sn-0.7 Cu) on Cu", J. Mater. Res., 17, 2 (2002).
  17. J. S. Ha, T. S. Oh and K. N. Tu, "Effect of Supersaturation of Cu on Reaction and Intermetallic Compound Formation between Sn-Cu Solder and Thin Film Metallization", J. Mater. Res., 18, 2109 (2003). https://doi.org/10.1557/JMR.2003.0296
  18. J. W. Yoon and S. B. Jung, "Effect of Isothermal Aging on Intermetallic Compound Layer Growth at The Interface between Sn-3.5 Ag-0.75 Cu Solder and Cu Substrate", J. Mater. Sci., 39, 13 (2004).
  19. S. K. Kang, W. K. Choi, D. Y. Shih, D. W. Henderson, T. Gosselin, A. Sarkhel, C. Goldsmith and K. J. Puttlitz, "$Ag_3Sn$ Pate Formation in the Solidification of Near-ternary", J. Mater., 55, 61 (2003).
  20. K. Zeng, R. Stierman, T. C. Chiu, D. Edwards, K. Ano and K. N. Tu, "Kirkendall Void Formation in Eutectic Sn-Pb Solder Joint on Bare Cu and Its Effect on Joint Reliability", J. Appl. Phys., 97, 024508 (2005). https://doi.org/10.1063/1.1839637
  21. J. M. Koo, B. Q. Vu, Y. N. Kim, J. B. Lee, J. W. Kim, D. U. Kim, J. H. Moon and S. B. Jung, "Mechanical and Electrical Properties of Cu/Sn-3.5Ag/Cu Ball Grid Array (BGA) Solder Joints after Multiple Reflows", J. Electron. Mater., 37, 118 (2008). https://doi.org/10.1007/s11664-007-0301-7
  22. N. Boyard, A. Millischer, V. Sobotka, J. Bailleul and D. Delaunay, "Behaviour of a Moulded Composite Part: Modelling of Dilatometric Curve (Constant Pressure) or Pressure (Constant Volume) with Temperature and Conversion Degree Gradients", Composites Sci. Technol., 67, 943 (2007). https://doi.org/10.1016/j.compscitech.2006.07.004
  23. S. Y. Yang, Y. Jeon, S. Lee and K. Paik, "Solder Reflow Process Induced Residual Warpage Measurement and Its Influence on Reliability of Flip-chip Electronic Packages", Microelectron. Reliab., 46, 512 (2006). https://doi.org/10.1016/j.microrel.2005.06.007
  24. S. Michaelides and S. K. Sitaraman, "Die Cracking and Reliable Die Design for Flip-chip Assemblies", IEEE Trans. Adv. Packag., 22, 602 (1999). https://doi.org/10.1109/6040.803452
  25. Y. Sawada, K. Harada and H. Fujioka, "Study of Package Warp Behavior for High-performance Flip-chip BGA", Microelectron. Reliab., 43, 465 (2003). https://doi.org/10.1016/S0026-2714(02)00294-9

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