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Thermo-Mechanical Reliability of TSV based 3D-IC

TSV 기반 3차원 소자의 열적-기계적 신뢰성

  • Yoon, Taeshik (Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST)) ;
  • Kim, Taek-Soo (Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST))
  • 윤태식 (한국과학기술원 기계공학과) ;
  • 김택수 (한국과학기술원 기계공학과)
  • Received : 2017.03.08
  • Accepted : 2017.03.21
  • Published : 2017.03.31

Abstract

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

Keywords

References

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