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Effect of Si grinding on electrical properties of sputtered tin oxide thin films

Si 기판의 연삭 공정이 산화주석 박막의 전기적 성질에 미치는 영향 연구

  • Cho, Seungbum (Graduate School of Nano-IT Design Convergence, Seoul National University of Science and Technology) ;
  • Kim, Sarah Eunkyung (Graduate School of Nano-IT Design Convergence, Seoul National University of Science and Technology)
  • 조승범 (서울과학기술대학교 나노IT디자인융합대학원) ;
  • 김사라은경 (서울과학기술대학교 나노IT디자인융합대학원)
  • Received : 2018.04.10
  • Accepted : 2018.06.22
  • Published : 2018.06.30

Abstract

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.

최근 유연 소자, 투명 소자, MEMS 소자와 같은 다양한 소자를 결합하는 시스템 집적화 기술이 많이 개발되고 있다. 이러한 다종 소자 시스템 제조 기술의 핵심 공정은 칩 또는 웨이퍼 레벨의 접합 공정, 기판 연삭 공정, 그리고 박막 기판 핸들링 기술이라 하겠다. 본 연구에서는 Si 기판 연삭 공정이 투명 박막 트랜지스터나 유연 전극 소재로 적용되는 산화주석 박막의 전기적 성질에 미치는 영향을 분석하였다. Si 기판의 두께가 얇아질수록 Si d-spacing은 감소하였고, Si 격자 내에 strain이 발생하였다. 또한, Si 기판의 두께가 얇아질수록 산화주석 박막 내 캐리어 농도가 감소하여 전기전도도가 감소하였다. 얇은 산화 주석 박막의 경우 전기전도도는 두꺼운 산화 주석 박막보다 낮았으며 Si 기판의 두께에 의해 크게 변하지 않았다.

Keywords

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