Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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The Method of Parallel Test Efficiency Improvement using Multi-Clock Mode

멀티클럭 모드를 이용한 병렬 테스트 성능 향상 기법

  • Hong, Chan Eui (Hoseo University, School of Electronics and Display Engineering) ;
  • Ahn, Jin-Ho (Hoseo University, School of Electronics and Display Engineering)
  • 홍찬의 (호서대학교 전자디스플레이공학부) ;
  • 안진호 (호서대학교 전자디스플레이공학부)
  • Received : 2019.08.31
  • Accepted : 2019.09.25
  • Published : 2019.09.30
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Abstract

In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.

Keywords

References

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