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Single-Phase Step-Up Five-Level Inverter with Phase-Shifted Pulse Width Modulation

  • Chen, Jianfei (School of Electrical Engineering, Chongqing University) ;
  • Wang, Caisheng (Department of Electrical and Computer Engineering, Wayne State University) ;
  • Li, Jian (School of Electrical Engineering, Chongqing University)
  • Received : 2018.05.19
  • Accepted : 2018.11.06
  • Published : 2019.01.20

Abstract

A single-phase step-up five-level inverter topology with a new phase-shifted pulse width modulation (PS-PWM) strategy is proposed in this paper. When compared with conventional single-phase five-level inverter topologies, the proposed topology can realize multilevel inversion with a double step-up ratio, a reduced number of switching devices and self-balanced capacitor voltages. When compared with the conventional PS-PWM strategy, the new PS-PWM strategy can be implemented with one carrier reduced, which makes it much easier to implement in a digital signal processor (DSP) system. Experimental results have been presented to verify the effectiveness of the proposed inverter and the PS-PWM strategy.

Keywords

I. INTRODUCTION

Single-phase multilevel inverters have received increasing attention due to their interesting features such as low harmonic currents and low voltage stresses across switching devices. As the output voltage level increases, the output harmonic content of inverters decreases, which allows for the use of smaller and less expensive output filters. Single-phase five-level inverters are widely used single-phase multilevel topology. The single-phase five-level inverter was first proposed by cascading two H-bridge inverters (CHB) to produce a five-level waveform [1], [2]. However, eight switches and their corresponding drivers are necessary for the circuit. Moreover, two split dc sources are needed, which can result in voltage-imbalance issues that should be carefully studied [3]. A single-phase full-bridge five-level neutral-point potential clamped (NPC) inverter and an improved version of the inverter have been proposed in [4]. Both of the circuits have only one dc source, which reduces the cost when compared with CHB. An improved modulation strategy has been proposed to achieve voltage-balance control for the two split capacitor voltages in the single-phase active NPC (ANPC) [5]. In [6], a single-phase five-level inverter comprising an asymmetric flying-capacitor H-bridge with a novel PWM scheme was proposed. Although improved output waveforms, a small filter size and low total harmonics distortion (THD) can be achieved by the circuit in [6], a pre-charging problem increases the complexity of the modulation strategy due to the flying-capacitor. To reduce the number of switches, an alternative five-level inverter was proposed in [7] and further studied and improved in [8-10]. Only five switches are needed in these newly proposed inverters, which simplifies the corresponding drive circuits. However, there are four diodes in the circuit of each type of inverter, which is not helpful for improving efficiency.

Single-phase five-level inverter topologies employing a coupled-inductor technique were proposed in [11]-[13]. The drawback of these circuits is that the coupled inductors need to be carefully designed. In addition, the five-level ANPC with coupled inductors in [12] has many switches. A simplified single-phase multistring five-level inverter was proposed in [14], [15]. Although the circuit can have a smaller number of components and can achieve a high efficiency, the two dc link capacitors are not connected in series, which requires two front step-up dc/dc converters or separate input sources. This increases the cost of the whole two-stage dc/ac power conversion system. A five-level inverter consisting of only six switches was proposed to achieve five-level PWM operation without clamping diodes or flying capacitors [16]. However, four active switches endure full dc-bus voltage stress with a high frequency in this topology. Recently, an enhanced single-phase step-up five-level inverter was proposed in [17]. This inverter was based on the switched-diode-capacitor cell presented in [18]. When compared with conventional five-level inverters, the inverter in [17] can realize multilevel inversion with a high step-up output voltage and a simple structure, which is mostly attributed to the switched-diode-capacitor cell. However, additional power switches and diodes are necessary and the corresponding modulation strategy is complicated.

A new single-phase five-level inverter topology with a new PS-PWM strategy is proposed in this paper. A self-balanced function for the capacitor voltages and a two-time step-up function are integrated in the new topology with a reduced number of power components. Four switches operate at a high frequency with low voltage stresses, while the other two switches operate at the line frequency (50 Hz) with high voltage stresses. The proposed PS-PWM strategy could use fewer triangular carriers to achieve the same performance as the conventional PS-PWM strategy.

II. PROPOSED INVERTER

Fig. 1 shows the proposed single-phase five-level inverter. As shown in this figure, there are six active switches, two diodes, and one dc source with two separate capacitors. The power switches S1 and S2 complement each other; as do the switches S3 and S4, and S5 and S6. Therefore, there are three independent active switches S1, S4 and S6. In Fig. 1, UC1 and UC2 represent the two split capacitor voltages, Uin represents the input voltage and uo represents the output voltage. In addition, the two split capacitors have the same capacitance.

 \(C_1 = C_2\)       (1)

E1PWAX_2019_v19n1_134_f0001.png 이미지

Fig. 1. Proposed single-phase step-up five-level inverter.

To some extent, the two capacitor voltages UC1 and UC2 remain stable. However, they fluctuate frequently due to the charging and discharging of the capacitors. Therefore, Table I gives the charge and discharge states of the two capacitors C1 and C2. Due to the symmetry of the sine wave reference, the charging time of C1 is the same as that of C2, i.e., the conduction time of S2 is the same as that of S1.

TABLE I SWITCHING COMBINATIONS

E1PWAX_2019_v19n1_134_t0001.png 이미지

For the proposed inverter, the two switches S5 and S6 are operated at the line frequency, while the other switches are operated at a high switching frequency. Based on the states of the switches, there are eight valid switching combinations that generate the required five output levels as shown in Table I. The corresponding operation stages of the five-level inverter are given in Fig. 2. For the convenience of the illustration, the switching function of the switches in Table I is defined as follows:

 \(S_{i}=\left\{\begin{array}{ll} 1 & S_{i} \text { is on } \\ 0 & S_{i} \text { is off } \end{array}, i=1,2 \ldots 6\right.\)       (2)

E1PWAX_2019_v19n1_134_f0002.png 이미지

Fig. 2. Operating stages: (a) I; (b) II; (c) III; (d) IV; (e) V; (f) VI;(g) VII; (h) VIII.

The eight operating stages of the proposed inverter are given in Fig. 2 and described in details as follows.

1) Maximum positive output level (UC1+UC2) (Stage I): in Stage I, the switches S2, D1, S3 and S6 are ON, and all of the other switches are off. The total voltage (UC1+UC2) is applied to the LC output filter, and the capacitor C1 is charged by the input source Uin.

2) Half positive output level Uin or UC2 (Stages II and III): one switching combination shown in Stage II is such that the switches S2, D1, S4 and S6 are ON. The other switching combination is such that the switches S1, D2, S3 and S6 are ON. During Stage II, the voltage UC2 is applied to the LC output filter and the capacitor C1 is charged by Uin simultaneously. During Stage III, Uin is applied to the LC filter and charges the capacitor C2.

3) Zero output level (Stages IV and V): in Stage IV, the switches S1, D2, S4 and S6 are ON. In Stage V, the switches D1, S2, S3 and S5 are ON. During these two stages, zero voltage is applied to the LC output filter. The capacitor C2 is charged by Uin during Stage IV and the capacitor C1 is charged by Uin during Stage V.

4) Half negative output level Uin or -UC1 (Stages VI and VII): one switching combination shown in Stage VI is such that the switches D1, S2, S4 and S5 are ON. The other switching combination shown in Stage VII is such that the switches S1, D2, S3 and S5 are ON. During Stage VI, -Uin is applied to the LC output filter and the capacitor C1 is charged by Uin simultaneously. During Stage VII, -UC1 is applied to the LC output filter and the capacitor C2 is charged by Uin simultaneously.

5) Maximum negative output level -(UC1+UC2) (Stage VIII): in Stage VIII, the switches S1, D2, S4 and S5 are ON, and the total voltage -(UC1+UC2) is applied to the LC output filter. In addition, the capacitor C2 is charged by the input source Uin.

The two split capacitor voltages are self-balanced by the input voltage source Uin, i.e.:

\(U_{C1}=U_{C2}=U_{in}\)       (3)

III. PS-PWM METHOD

For a multilevel inverter, the logic relationship among the drive signals of the switches, carrier signals and modulation signals should be achieved before selecting a certain modulation strategy. In the proposed inverter, with three pairs of complementary switches, it is only necessary to determine the logic relation among the drive signals of three switches, carrier signals and modulation signals. In this section, the eight switching combinations in Table I are rewritten in Table II with A, B and C to generate a five-level voltage waveform. A, B and C represent the outputs of the three comparators, which are also given in Fig. 5.

TABLE II TRUTH TABLE

E1PWAX_2019_v19n1_134_t0002.png 이미지

To determine the relations among A, B and C and S1, S4 and S6, three Karnaugh maps for the switches S1, S4 and S6 are presented in Fig. 3. According to Fig. 3, it is not difficult to obtain the logic relations shown in (4). The next step is to select a modulation strategy for the inverter.

 \(\left\{\begin{array}{l} S_{1}=A \bar{B}+\bar{A} B=A \oplus B \\ S_{4}=A \bar{C}+\bar{A} C=A \oplus C \\ S_{6}=A \end{array}\right.\)       (4)

E1PWAX_2019_v19n1_134_f0003.png 이미지

Fig. 3. Karnaugh maps for S1, S4 and S6.

For a multilevel inverter, carrier-based phase disposition pulse width modulation (PD-PWM) is a common strategy. As shown in Fig. 4(a), the PD-PWM strategy is implemented by using four triangular carriers and one reference signal. Four carriers with the same frequency, amplitude and phase angle are disposed as the upper and lower four layers, labelled as C1(t), C2(t), C3(t) and C4(t), which are symmetrically distributed in the two-side of the horizontal axis, and compared with a sine modulation wave m(t). However, it is difficult to produce so many triangular carriers with the phase disposition in a DSP control board. In addition, a lot of triangular carriers drain the computing resources of the DSP. Therefore, it is desirable to take a modulation strategy with a reduced number of triangular carriers that can achieve the same or much better output performance than the conventional PD-PWM strategy.

E1PWAX_2019_v19n1_134_f0004.png 이미지

Fig. 4. Switching patterns of PD-PWM strategies: (a) Conventional PD-PWM; (b) Optimal PD-PWM.

Referring to the modulation strategy in [17], [21], an optimal PD-PWM strategy with only two triangular carriers can be used to generate switching signals for the proposed inverter. The switching patterns of the inverter with the optimal PD-PWM strategy are presented in Fig. 4(b), where the two triangular carrier signals C1(t) and C2(t) have the same frequency, amplitude, and phase angle. The same output performance as the conventional PD-PWM can be achieved. However, it is still difficult to produce two triangular carriers with phase disposition in a DSP control board.

Another interesting strategy is phase-shifted pulse width modulation (PS-PWM) and its logic relation, shown in Fig. 5(a), is similar to that in the optimal PD-PWM. A small difference between them is that the two triangular carriers C1(t) and C2(t) in the PS-PWM strategy are phase-shifted 180 degrees instead of phase disposition. In Fig. 5(a), the reference sinewave m(t) is used to compare with zero for zero-crossing detection and for providing the line frequency switching signals for S5 and S6. The absolute value of the sinewave |m(t)| is used for comparison with the triangular carrier signals C1(t) and C2(t) to provide switching signals for the other four switches S1-S4.

E1PWAX_2019_v19n1_134_f0005.png 이미지

Fig. 5. Modulation logic diagram of PD-PWM strategies: (a)Conventional PS-PWM; (b) Proposed PS-PWM.

Producing two phase-shifted triangular carriers is a lot easier than producing two carriers with phase disposition in a DSP control board system. The switching patterns of an inverter with the conventional PS-PWM strategy was given in Fig. 6. By comparing Fig. 5(a) and Fig. 6(a), it can be found that the equivalent switching frequency of the output voltage using the PS-PWM strategy is two times that using the PD-PWM strategy or the optimal PD-PWM strategy. As a result, the output harmonic component can be largely reduced and the output filter can be designed with a smaller size by using the PS-PWM strategy. That is why the PS-PWM strategy is widely used in power converters.

E1PWAX_2019_v19n1_134_f0006.png 이미지

Fig. 6. Switching patterns of PS-PWM strategies: (a) Conventional PS-PWM; (b) Proposed PS-PWM.

In this paper, a new PS-PWM strategy is proposed using only one triangular carrier C1(t) as shown in Fig. 5(b). In addition, its switching patterns are given in Fig. 6(b). Like the conventional PS-PWM strategy, the drive signals of S1 and S4 are phase-shifted 180 degrees. The same output performance as the conventional PS-PWM strategy can be achieved with one carrier reduced, which makes it a lot easier to implement in a DSP control board system. In the proposed PS-PWM strategy, the two reference waves m1(t) and m2(t) given in (5) are needed and it can be considered that m2(t) is achieved by rotating m1(t) 180 degrees. It is easy to produce m1(t) and m2(t) in a DSP control board.

\(\left\{\begin{array}{l} m_{1}(t)=|m(\mathrm{t})| \\ m_{2}(t)=1-|m(\mathrm{t})| \end{array}\right.\)       (5)

In the proposed PS-PWM modulation strategy, the triangular carrier C1(t) is used for comparison with m1(t) and m2(t) to generate the switching signals for S1 and S4. Unlike the conventional PS-PWM strategy, the comparing logic for obtaining C (i.e., the output of the third comparator in Fig. 5(b)) in the proposed PS-PWM strategy is contrary to that of the conventional PS-PWM strategy. The second triangular carrier C2(t) is not necessary in the proposed PS-PWM strategy. On the whole, the proposed PS-PWM strategy is easier to implement while guaranteeing the same inverter performance as the conventional PS-PWM strategy.

IV. PERFORMANCE ANALYSIS

A. Integration of Self-Balanced and Step-Up Function

It is easy to show that the two capacitors C1 and C2 are charged and discharged, as reported in [18]-[20]. Equivalent circuits of the switched-diode-capacitor network are presented in Fig. 7. It can be seen that when the switch S1 is on, the capacitor C2 is charged by the input source Uin through the diode D2. It can also be seen that when S2 is on, the capacitor C1 is charged by the input source Uin through the diode D1. Considering the voltage drops of the diodes, C1 is charged at Uin-UD1 and C2 is charged at Uin-UD2. In the proposed topology, the two diodes D1 and D2 have the same characteristics and they are the same kind of diode in the experiment. Thus, the difference between UD1 and UD2 is very small even when considering practical parasitic parameters. In addition, the difference between C1 and C2 only influences their voltage ripples but does not influence their average voltages. Therefore, there is no need to consider the neutral-point potential issue in this five-level inverter. Since there are idle states of the two capacitors, enough capacitance is provided to ensure stable capacitor voltages.

E1PWAX_2019_v19n1_134_f0007.png 이미지

Fig. 7. Equivalent circuits of the switched-diode-capacitor cell:(a) S1 is on, S2 is off; (b) S1 is off, S2 is on.

Considering that the reference wave m(t) is equal to msin(2πfmt), the output voltage uo (RMS value) can be expressed as follows:

\(u_{o}=\left(U_{C 1}+U_{C 2}\right)* m \sin \left(2 \pi f_{m} t\right) / \sqrt{2}=\sqrt{2} m U_{i n} \sin \left(2 \pi f_{m} t\right)\)       (6)

Where fm is the line frequency and m is the modulation index that is expressed by:

\(m=\frac{A_{m}}{2 A_{c}}\)       (7)

Therefore, the step-up ratio of the inverter can be defined as:

\(\frac{u_{o}}{U_{i n}}=\sqrt{2} m \sin \left(2 \pi f_{m} t\right)\)       (8)

It can be concluded from (8) that the proposed inverter has step-up capacity and that the step-up ratio is two times that of the conventional single-phase two-level inverter.

B. Loss Analysis

According to the theoretical analysis above, the two switches S5 and S6 experience voltage stresses equaling to 2Uin while the other four switches S1-S4 experience voltage stresses equal to Uin. In addition, a great advantage of the proposed topology is a self-balancing function for capacitor voltages. As shown in Table II and Fig. 2, the two capacitors C1 and C2 are charged and discharged for the same period during a whole fundamental switching cycle. As a result, the two capacitor voltages are self-balanced. Meanwhile, a two-time step-up ratio is achieved.

When the modulation index m is less than or equal to 1/2, the inverter outputs three voltage levels while the two capacitors C1 and C2 are kept idle under this condition. When m is over 1/2, the capacitor voltage waveform during one fundamental period is presented in Fig. 8, in which there is:

 \(\begin{array}{l} \theta_{1}=\sin ^{-1}\left(A_{c} / A_{m}\right) \\ \theta_{2}=\pi-\sin ^{-1}\left(A_{c} / A_{m}\right) \\ \theta_{3}=\pi \\ \theta_{4}=\pi+\sin ^{-1}\left(A_{c} / A_{m}\right) \\ \theta_{5}=2 \pi-\sin ^{-1}\left(A_{c} / A_{m}\right) \\ \theta_{6}=2 \pi \end{array}\)       (9)

E1PWAX_2019_v19n1_134_f0008.png 이미지

Fig. 8. Capacitor voltages during one fundamental period.

Thus, the time period △t in which the voltage of C1 or C2 decreases can be expressed as follows:

\(2 \pi f_{m} \Delta t=\theta_{2}-\theta_{1}\)       (10)

According to (7), (9) and (10), △t can be obtained by:

\(\Delta t=\frac{1}{2 f_{m}}-\frac{\sin ^{-1}(1 /(2 m))}{\pi f_{m}}\)       (11)

Therefore, the voltage across C1 or C2 can be obtained by:

\(u_{c}=U_{C \max } \mathrm{e}^{-\frac{2 t}{R C}}, 0<\mathrm{t}<\Delta \mathrm{t}\)       (12)

Where R and C are the output load and the capacitance of C1 and C2. It can be concluded from Fig. 2 that the capacitor C1 is charged when S2 and D1 are turned on, and that the capacitor C2 is charged when S1 and D2 are turned on. For simplicity, the diodes D1 and D2 are assumed to have a voltage drop of UD. By ignoring the on-state resistance of the power switches and parasitic resistors in the circuit, the maximum capacitor voltage across C1 and C2 can be calculated as follows:

\(U_{C \max }=U_{i n}-U_{D}\)       (13)

Therefore, as shown in Fig. 9, the capacitor voltages of C1 and C2 can be calculated by:

\(u_{c}=\left(U_{i n}-U_{D}\right) \mathrm{e}^{-\frac{2 t}{R C}}, 0<\mathrm{t}<\Delta \mathrm{t}\)       (14)

E1PWAX_2019_v19n1_134_f0009.png 이미지

Fig. 9. Switching states according to the relative position between the modulation signal and the carrier signal during Ts.

In addition, the voltage ripple of C1 or C2 can be estimated based on (11) and (14).

\(\Delta u_{c}=U_{C \max }-U_{C \min }=\left(U_{i n}-U_{D}\right)\left(1-\mathrm{e}^{\frac{2 \sin ^{-1}(1 /(2 m))}{\pi f_{m} R C}\frac{1}{f_{m} R C}}\right)\)       (15)

It can be seen from (15) that the voltage variation of the capacitor is related to the fundamental frequency fm, modulation index m, output load R and capacitance C.

For switched-capacitor inverters, there are three types of power losses, including switching losses, conduction losses and capacitor distribution losses. In capacitor charging or discharging cycles, capacitor distribution losses are produced due to the voltage difference between the capacitors. Reference [22] indicates that the distribution losses are directly proportional to the capacitance and the capacitor voltage ripple. Thus, the capacitor distribution losses can be estimated by:

\(P_{d i s}=f_{s} * \frac{1}{2} C\left(\frac{\Delta u_{c}}{2}\right)^{2} * 2=\frac{1}{4} f_{s} C \Delta u_{c}^{2}\)       (16)

Where fs is the switching frequency.

The conduction loss is caused by the parasitic parameters, including the on-state resistances of the switches and the forward voltage drops of the diodes. For the main power circuit with a load R, there are two different conduction paths. Fig. 9 shows the switching states according to their relative position between the modulation signal and the carrier signal during one switching period Ts. Since Ts is much shorter than the fundamental period, the modulation signal can be deemed as a straight horizontal line during Ts. In this way, the on-state ratio k1 in the operating states of Fig. 2(b)-(g), and the on-state ratio k2 in the operating states of Fig. 2(a) and Fig. 2(h), can be obtained.

\(\frac{2 m A_{c} \sin \theta}{A_{c}-0}=\frac{k_{1} T_{s}}{T_{s}} \Rightarrow k_{1}=2 m \sin \theta\left(0<\theta<\theta_{1}, \theta_{2}<\theta<\theta_{4}, \theta_{5}<\theta<\theta_{6}\right)\)       (17)

\(\frac{2 m A_{c} \sin \theta-A_{c}}{2 A_{c}-A_{c}}=\frac{k_{2} T_{s}}{T_{s}} \Rightarrow k_{2}=2 m \sin \theta-1\left(\theta_{1}<\theta<\theta_{2}, \theta_{4}<\theta<\theta_{5}\right)\)       (18)

For the operating states of Fig. 2(b), (c), (f) and (g), three switches are conducted with the conduction loss:

\(P_{c o n_{-} 1}=\frac{1}{\pi}\left(\int_{0}^{\theta_1} d \theta+\int_{\theta_{2}}^{\theta_{4}} d \theta+\int_{\theta_{5}}^{\theta_{6}} d \theta\right) *\left(\frac{U_{i n}-u_{a b}}{3 r_{o n}+R}\right)^{2} * 3 r_{o n} * k_{1}\)       (19)

For the operating states of Fig. 2(a) and Fig. 2(h), two switches and one diode are conducted, and the conduction loss can be calculated by:

\(P_{\text {con}_{-}2}=\frac{1}{\pi}\left(\int_{\theta_1}^{\theta_{2}} d \theta+\int_{\theta_{4}}^{\theta_{5}} d \theta\right)*\left[\left(\frac{2 U_{\text {in}}-u_{a b}}{2 r_{o n}+R}\right)^{2} * 2 r_{o n}+\frac{2 U_{\text {in}}-u_{a b}}{2 r_{o n}+R} U_{D}\right]* k_{2}\)       (20)

According to (17)-(20), the total conduction losses of the proposed inverter can be calculated by:

\(\begin{array}{l} P_{con}=P_{con_{-}1}+P_{con_{-} 2}=\frac{1}{\pi}\left[\left(\frac{U_{i n}-u_{ab}}{3 r_{o n}+R}\right)^{2} * 24 \mathrm{m}r_{on} *(1-\sqrt{1 \frac{1}{4 m^{2}}})+\right. \\ {\left[4 \mathrm{m} \sqrt{1 - \frac{1}{4 m^{2}}}-\pi+2 \sin ^{-1}\left(\frac{1}{2 m}\right)\right]*\left[\left(\frac{2 U_{i n}-u_{ab}}{2 r_{o n}+R}\right)^{2} * 4 r_{o n}+\frac{2 U_{i n}-u_{ab}}{2 r_{o n}+R} * U_{D}\right]} \end{array}\)       (21)

The switching loss can be estimated from the charging and discharging processes of the parasitic capacitance between the drain terminal and the source terminal. Due to the phase-shift modulation, the equivalent switching frequency is doubled. Thus, the switching loss can be estimated by:

\(P_{s w}=2 f_{s} * C_{d s} V_{b}^{2}\)       (22)

Where Cds and Vb are the parasitic capacitance and the maximum block voltage of each switch. The block voltages of S1-S4 are all equal to Uin, and the block voltages of S5 and S6 are equal to 2Uin. Therefore, the total switching loss of the proposed inverter can be calculated by:

\(P_{s w}=2\left[f_{s}^{*} C_{ds 1} * 4 * U_{i n}^{2}+f_{m} * C_{ds2} * 2 *\left(2 U_{i n}\right)^{2}\right]=\left(8 f_{s} C_{ds1}+16 f_{m} C_{ds2}\right) U_{i n}^{2}\)       (23)

Where Cds1 is the parasitic capacitance of S1-S4 and Cds2 denotes the parasitic capacitance of S5-S6. Finally, the total power losses of the proposed inverter can be calculated by:

\(P_{total}=P_{dis}+P_{con}+P_{sw}\)       (24)

C. Comparative Analysis

As previously mentioned, many single-phase five-level inverter topologies have been proposed. In this section, Table III summarizes comparisons between popular five-level inverters and the proposed inverter. In Table III, S, D, C and L represent the quantities of the switches, diodes, capacitors, and inductors used in the topologies. It can be observed that only five active switches are needed and that four diodes are added for the inverters reported in [7]-[10], which may increase the conduction losses of the inverters. The topology in [14], [15] has the lowest number of power components. However, two split dc sources are necessary, which greatly limits its application. A new hybrid five-level inverter was developed in [16] without clamped diodes or capacitors. The topology is simple with only six power switches. When compared with the hybrid five-level inverter, two more diodes are needed in the proposed inverter. However, under the same output voltage conditions, only two power switches in the proposed inverter bear a high voltage stress while four power switches in the inverter of [16] bear a high voltage stress. Moreover, only UC2 in the topology of [16] helps contribute to achieving the two voltage levels +0.5Uin and -0.5Uin, while UC1 remains idle expect for contributing to achieving the two voltage levels Uin and -Uin together with UC2. This is the basic reason for an imbalanced potential issue, and a voltage-balance control strategy is necessary. However, this issue does not exist in the proposed five-level inverter because both UC1 and UC2 in the proposed topology help in achieving the two voltage levels +0.5Uin and -0.5Uin. The two capacitor voltages are self-balanced during the modulation process. Therefore, there is no need to consider voltage-balance control strategies for the proposed topology.

TABLE III COMPARISON ANALYSIS

E1PWAX_2019_v19n1_134_t0003.png 이미지

All of these topologies, except the topology in [17] and the proposed topology in this paper, have a common neutral-point potential imbalance issue. The modulation strategies of these topologies should accurately balance the charging time for each of the capacitors for realizing the voltage-balance goal. However, this makes the modulation strategies more complicated. On the other hand, neutral-point potential imbalance is not an issue for the topology in [17] or the proposed topology due to the self-balanced function of the switched-diode-capacitor cell. The integration of the front step-up circuit and the back inversion circuit in [17] is a good advantage. However, it results in a complicated modulation scheme since the step-up function and inversion function should be considered simultaneously. Moreover, the proposed inverter in this paper has one less inductor and one less diode when compared with the topology in [17]. The proposed PS-PWM strategy makes it much easier to implement in an actual control system. Hence, the proposed topology is simpler and easier to implement.

On the whole, the double function of dc-dc step-up conversion with a two-time ratio and dc-ac inversion with a simple modulation strategy is realized in the proposed five-level inverter. On the one hand, one dc source with a reduced number of power switches and small voltage stresses are achieved. On the other hand, a new PS-PWM strategy with one carrier is proposed, and it is easy to implement in DSP control board systems. All of these merits make it superior to existing five-level inverters.

D. Closed-Loop Control

The closed-loop implementation of the inverter is based on a proportional resonant (PR) controller with a resonant peak at the fundamental frequency 50Hz. An overall block diagram of the control scheme is presented in Fig. 10, and the PR controller structure is given as:

 \(G(\mathrm{s})=k_{p}+\frac{2 k_{r} \omega_{c} s}{s^{2}+2 \omega_{c} s+\omega_{o}^{2}}\)       (25)

 E1PWAX_2019_v19n1_134_f0017.png 이미지

Fig. 10. Overall block diagram of the control scheme.

Where kp is the proportional gain, kr is the resonant gain, ωc is the cut-off frequency, and ωo is the fundamental radian frequency. The resonant gain of the PR controller will only integrate frequencies very close to the fundamental frequency and will not introduce stationary error or phase shift [23], [24]. Using the PR controller, reference tracking performance can be enhanced and the known drawback of a PI controller that the steady-state errors in the single-phase system can be alleviated.

According to the bilinear transformation (9) in [25], the expression (8) could be discretized as (10).

\(s=\frac{2}{T} \frac{1-z^{-1}}{1+z^{-1}}\)       (26)

\(G(z)=\frac{b_{0}+b_{1} z^{-1}+b_{2} z^{-2}}{a_{0}+a_{1} z^{-1}+a_{2} z^{-2}}\)       (27)

Where 1/T means the control frequency of the PR controller and a0, a1, a2, b0, b1 and b2 are:

\(\left\{\begin{array}{l} a_{0}=1 \\ a_{1}=\frac{2 \omega_{0}^{2} T^{2}-8}{\omega_{0}^{2} T^{2}+4 \omega_{c} T+4} \\ a_{2}=\frac{\omega_{0}^{2} T^{2}-4 \omega_{c} T+4}{\omega_{0}^{2} T^{2}+4 \omega_{c} T+4} \\ b_{0}=\frac{k_{p}\left(\omega_{0}^{2} T^{2}+4 \omega_{c} T+4\right)+4 k_{r} \omega_{c} T}{\omega_{0}^{2} T^{2}+4 \omega_{c} T+4} \\ b_{1}=k_{p} a_{1} \\ b_{2}=\frac{k_{p}\left(\omega_{0}^{2} T^{2}-4 \omega_{c} T+4\right)-4 k_{r} \omega_{c} T}{\omega_{0}^{2} T^{2}+4 \omega_{c} T+4} \end{array}\right.\)       (28)

Therefore, a difference equation is obtained as follows:

\(u(k)=-\frac{a_{1}}{a_{0}} u(k-1)-\frac{a_{2}}{a_{0}} u(k-2)+\frac{b_{0}}{a_{0}} e(k)+\frac{b_{1}}{a_{0}} e(k-1)+\frac{b_{2}}{a_{0}} e(k-2)\)       (29)

In expression (29), u(k), u(k-1) and u(k-2) represent the output voltage signals at the moments k, k-1 and k-2. Meanwhile, e(k), e(k-1) and e(k-2) represent the corresponding error signals at the moments k, k-1 and k-2, respectively. The expression (29) can then be programmed into the DSP control board system to realize the PR control for stabilizing the output voltage of the proposed inverter.

V. EXPERIMENTAL VERIFICATION

To verify the correctness of the proposed topology and modulation method, an experimental prototype with a 150W output power, as shown in Fig. 11, has been built according to the parameters presented at Table IV. The controller is implemented based on a digital signal processor TMS320F28335.

E1PWAX_2019_v19n1_134_f0010.png 이미지

Fig. 11. Experimental prototype.

TABLE IV EXPERIMENTAL PARAMETERS

E1PWAX_2019_v19n1_134_t0004.png 이미지

It should be noted that a three-phase LC filter board and a three-phase voltage-current sensor board are presented in the prototype picture. However, a single-phase LC filter and a single voltage sensor are used in the actual prototype. In the PR controller, kp is 0.0001, kr is 1.0, wc is 5rad/s, and wo is 314.15. Referring to [26], the inductor Lo is calculated as:

\(L_{o}=\frac{U_{i n}}{4 * f_{o} *\left(\frac{\sqrt{2} P_{o}}{u_{o}} * \eta\right)}\)       (30)

In (30), fo means the equivalent switching frequency of the output voltage uab, Po means the output power, and ƞ means current ripple percentage. In the experiment, ƞ is selected as 20%. With a switching frequency of 10 kHz, the equivalent switching frequency fo of the output voltage uab should be 20 kHz due to the PS-PWM strategy. According to the experimental parameters and (30), the inductor Lo is 1.06mH. In the prototype, the inductor is selected as 1.0mH. On the other hand, the cut-off frequency fcut of the output LC filter is usually regarded as ten percent of the switching frequency of the output voltage Vab, i.e., 2kHz.

\(f_{c u t}=\frac{1}{2 \pi \sqrt{L_{o} C_{o}}}=2.0 k H z\)       (31)

According to (31), the output capacitor Co can be calculated as 6.3uF. Therefore, the inductance and capacitance of the LC filter are 1.0mH and 6.3uF.

Comparison results of the conventional PS-PWM strategy and the proposed PS-PWM strategy are presented, including the key voltage waveforms in Fig. 12, the drive signals of S1, S4 and S6 in Fig. 13, the terminal voltage waveforms of the switches S1 and S4, and the output voltage in Fig. 14. It can be seen from Fig. 12 that the output voltage uab presents a five-level shape and that the output voltage uo presents a pure sine waveform. In addition, the two capacitor voltages are both nearly 60V, which is equal to the input voltage 60V. This verifies the correctness of the step-up capability and self-balance function. Low frequency capacitor voltage ripples are inevitable due to the charging and discharging of the capacitors. The drive signals of the switches in Fig. 13 show that the switches S1 and S4 have a 180 degrees difference in phase, which verifies the correctness of the proposed PS-PWM strategy. In Fig. 14, the output voltage is composed of a 20 kHz PWM voltage signal, which is two times of the switching frequency of S1 and S4. All of the comparison results in Figs. 12-14 verify the proposed PS-PWM strategy.

E1PWAX_2019_v19n1_134_f0011.png 이미지

Fig. 12. Key voltage waveforms: (a) Conventional PS-PWM; (b)Proposed PS-PWM.

E1PWAX_2019_v19n1_134_f0012.png 이미지

Fig. 13. Drive signals: (a) Conventional PS-PWM; (b) Proposed PS-PWM.

E1PWAX_2019_v19n1_134_f0013.png 이미지

Fig. 14. Terminal voltage waveforms of S1, S4, and the output voltage: (a) Conventional PS-PWM; (b) Proposed PS-PWM.

By comparing experimental results under the two different PS-PWM modulation strategies, it can be concluded that the proposed PS-PWM strategy has output performance equivalent to that of the conventional PS-PWM strategy. Thus, it can be claimed that the proposed PS-PWM strategy is equivalent to the conventional PS-PWM strategy in terms of inverter output performance. Since one triangular carrier is reduced, the proposed PS-PWM strategy is better than the conventional PS-PWM strategy in actual implementation. In fact, the proposed PS-PWM strategy can be used or extended to other power converter systems, such as a multi-phase dc/dc converter systems, cascaded multilevel converters, and modular multilevel converters. With the proposed PS-PWM strategy, half carriers can be saved and it becomes a lot easier to implement in a DSP.

Apart from the analysis mentioned above, it can be seen from Fig. 15 that all of the power components besides S5 and S6 endure half of the peak value of the output voltage. Although S5 and S6 endure the output peak voltage, the switching frequency for each of the switches is equal to the line frequency, which does not cause high switching losses. Moreover, the dynamic results of the inverter under a load step from 47 ohm to 23.5 ohm or vice versa are also given in Fig. 16. It can be seen that the output voltage is kept stable under the load step, and that the output current io increases by two times or half of its original value during a very short time, which indicates a very good dynamic response of the inverter.

E1PWAX_2019_v19n1_134_f0014.png 이미지

Fig. 15. Voltage waveforms of switches and diodes under the proposed modulation strategy: (a) D1, S1, S2, D2; (b) S3, S4, S5, S6.

E1PWAX_2019_v19n1_134_f0015.png 이미지

Fig. 16. Dynamic results under a load step.

Finally, the conversion efficiency of the inverter is presented in Fig. 17. The conversion efficiency of the inverter is over 95.27% at a light load and 91.19% at a full load (i.e., 23.5 ohm for the 150W power rating). As shown in Fig. 12, the voltage ripple Δuc of C1 or C2 is around 3.0V. The parasitic capacitance Cds1 of the switches S1-S4 (IRFP250) is 530pf, and the parasitic capacitance Cds2 of the switches S5-S6 (IRFP450) is 380pf. In addition, the conduction resistance of S1-S4 (IRFP250) is 0.085ohm, and the conduction resistance of S5-S6 (IRFP450) is 0.4ohm. The equivalent series resistance of C1 or C2 is 0.1ohm. Based on the parameters and the formulas (16), (21) and (23), the capacitor distribution loss, conduction loss and switching loss of the proposed inverter with a full power load are calculated as 8.58W, 4.26W and 0.16W. It can be found that the capacitor distribution loss dominates the total power loss, while the switching loss is the lowest. The conversion efficiency of the proposed inverter with a full load is 91.33%, which basically matches its tested value of 91.19%.

E1PWAX_2019_v19n1_134_f0016.png 이미지

Fig. 17. Conversion efficiency curve.

VI. CONCLUSION

A single-phase step-up five-level inverter has been proposed and implemented with a new PS-PWM strategy in this paper. The operating principle and performance analysis show that a double step-up ratio, reduced number of power devices and self-balanced capacitor voltages are achieved in the proposed inverter topology. Furthermore, the proposed PS-PWM strategy is equivalent to the conventional PS-PWM strategy with one less carrier, which makes it much easier to implement in a DSP control board system. The proposed PS-PWM strategy provides a new idea for implementing phase-shifted modulations and can be extended to other power converters. The PR control method was utilized to realize closed loop control for the output voltage of the proposed inverter.

ACKNOWLEDGMENT

This work was partially supported by China Postdoctoral Science Foundation under grant number 2017M612908 and partially supported by NSFC under award # U1609216.

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