Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

  • Kwen, Hyeunwoo (School of Electrical Engineering, Kyungpook National University) ;
  • Kim, Sang-Hwan (School of Electrical Engineering, Kyungpook National University) ;
  • Lee, Jimin (School of Electrical Engineering, Kyungpook National University) ;
  • Choi, Pyung (School of Electrical Engineering, Kyungpook National University) ;
  • Shin, Jang-Kyoo (School of Electrical Engineering, Kyungpook National University)
  • Received : 2020.03.13
  • Accepted : 2020.03.30
  • Published : 2020.03.31
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Abstract

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

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References

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